This brief presents a novel level-shifter circuit for high-frequency high-voltage (HV) gate-drives. The proposed level shifter (LS) is designed based on a capacitive-coupler/current mirror/ latch structure which helps to extend operation voltage of a floating supply into the negative range, achieves sub-ns and constant delay, and consumes very low power from the floating supply. Additionally, common-mode noise cancellers based on a cross-current mirror and transmission gates are also presented to enhance the dV/dt immunity of the LS against slewing of the floating ground. Implemented in 0.18 $\mu \text{m}$ HV BCD-on-SOI (bipolar-CMOS-DMOS on silicon-on-isolator) process, the post-layout simulation of the proposed design shows a delay of 680 ps, 200 V/ns of $\text{d}{V} _{\mathrm {SSF}}$ /dt slew rate immunity, It dissipates no static power and only 8.1 pJ/transition from the floating supply, improving FoM ¹ and FoM ² of the proposed LS by 3 times and 11.7 times compared to respective state-of-the-art works.

中文翻译：

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通用的200V电容耦合电平转换器，用于完全浮动的多MHz栅极驱动器

本简介介绍了一种用于高频高压（HV）栅极驱动器的新型电平转换器电路。拟议的电平转换器（LS）是基于电容耦合器/电流镜/锁存器结构设计的，该结构有助于将浮动电源的工作电压扩展到负范围，实现亚ns和恒定延迟，并消耗非常低的功耗。浮动供应。此外，还提出了一种基于交叉电流镜和传输门的共模噪声消除器，以增强LS的dV / dt抗扰度，使其免受浮地的回转影响。在0.18中实现 $ \ mu \ text {m} $ HV BCD-on-SOI（隔离硅上的双极CMOS-DMOS）工艺，提出的设计的布局后仿真显示，延迟为680 ps，200 V / ns $ \ text {d} {V} _ {\ mathrm {SSF}} $ / dt压摆率抗扰度，它不消耗静态功率，仅从浮动电源消耗8.1 pJ /跃迁，与相应的最新技术相比，所建议的LS的FoM ¹和FoM ^2分别提高了3倍和11.7倍。