Resistive memory (RRAM) provides an ideal platform to develop embedded non-volatile computing-in-memory (nvCIM). However, it faces several critical challenges ranging from device non-idealities, large DC currents, and small signal margins. To address these issues, we propose voltage-division (VD) based computing approach and its circuit implementation in two-transistor-two-resistor (2T2R) RRAM cell arrays, which can realize energy-efficient, sign-aware, and robust deep neural network (DNN) processing. A readout technique, namely the input-dependent sensing control (IDSC) scheme, is also introduced for power saving. On this basis, a 400kb VD-based RRAM nvCIM is silicon verified. It achieves 2.54 times power reduction compared to that of the ones rely on conventional weighted-current summation (WCS) mechanism, a peak energy-efficiency of 42.6 TOPS/W and a minimum latency of 15.98 ns.

中文翻译：

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具有输入相关感测控制的2T2R RRAM中基于分压的高效鲁棒非易失性内存计算

阻性存储器（RRAM）提供了开发嵌入式非易失性内存计算（nvCIM）的理想平台。但是，它面临着数个关键挑战，包括器件非理想性，较大的直流电流和较小的信号余量。为了解决这些问题，我们提出了基于分压（VD）的计算方法及其在两晶体管二电阻（2T2R）RRAM单元阵列中的电路实现，可以实现节能，符号感知和鲁棒的深度神经网络。网络（DNN）处理。还引入了一种读出技术，即依赖于输入的传感控制（IDSC）方案，以节省功耗。在此基础上，对基于400kb VD的RRAM nvCIM进行了硅验证。与传统的加权电流求和（WCS）机制相比，它的功耗降低了2.54倍，峰值能量效率为42。