Binarized convolutional neural network (BCNN) is a promising and efficient technique toward the landscape of Artificial Intelligence of Things (AIoT) applications. In-Memory Computing (IMC) has widely been studied to accelerate the inference task of BCNN to maximize both throughput and energy efficiency. However, existing IMC circuits and architectures are only optimized for a fixed kernel size and nominal voltage operation, which poses practical limitations on optimal network architecture exploration and additional energy efficiency benefits. In this brief, we present a reconfigurable, near-threshold IMC-based BCNN accelerator design. The IMC-based accelerator architecture is scalable for different kernels sizes ( $3 \times 3 \times d$ and $5 \times 5 \times d$ ) and achieves high resource utilization for both cases. Moreover, the IMC bitcell is optimized for reliable near-threshold operation. Implemented in a 55-nm CMOS process, our proposed reconfigurable IMC-based BCNN accelerator achieves 5526 TOPS/W energy efficiency at 0.4V, which is $6.38\times $ higher compared to the state-of-the-art designs. The inference accuracies of our proposed design are 97.73%, 82.56%, and 92.61% across three datasets (MNIST, CIFAR-10, and SVHN), respectively.

中文翻译：

---

适用于AIoT应用的55nm，0.4V 5526-TOPS / W内存中计算二进制CNN加速器

二进制卷积神经网络（BCNN）是面向人工智能（AIoT）应用领域的一种有前途且高效的技术。内存中计算（IMC）已被广泛研究以加速BCNN的推理任务，以最大化吞吐量和能效。但是，现有的IMC电路和体系结构仅针对固定的内核大小和标称电压操作进行了优化，这对优化网络体系结构的探索和附加的能效优势造成了实际限制。在本简介中，我们提出了一种可重新配置的，基于IMC的接近阈值的BCNN加速器设计。基于IMC的加速器体系结构可扩展为不同的内核大小（ $ 3 \时间3 \时间d $ 和 $ 5 \时间5 \时间d $ ），并在两种情况下都实现了较高的资源利用率。此外，IMC位单元已针对可靠的近阈值操作进行了优化。我们提出的可重构的基于IMC的BCNN加速器采用55 nm CMOS工艺实现，在0.4V时可达到5526 TOPS / W的能量效率，这是 $ 6.38 \次$ 与最新设计相比更高。我们提出的设计的推论准确性在三个数据集（MNIST，CIFAR-10和SVHN）中分别为97.73％，82.56％和92.61％。