This contribution proposes a technique for leakage power reduction in Dual Mode Logic (DML) circuits by incorporating Gated Leakage Transistor (GLT). The resulting circuits are named as GALEOR with Dual Mode Logic (GDML). Further, GDML design is extended by including a footed diode transistor, the design so obtained is referred to as GALEOR with Dual Mode Logic with footed diode (GDMLD). The analysis is done using footed type A and type B DML gates, resulting in GDML and GDMLD variants referred to as GDML-TA, GDML-TB, GDMLD-TA and GDMLD-TB. Two input NAND and NOR gates along with a full adder and a 2-bit multiplier circuit are used to investigate the proposed techniques at 90 nm and 45 nm technology nodes in both static and dynamic mode using SymicaDE tool. Analysis of leakage power reveals that its value increases with technology scaling. Average leakage power saving is 44.69%-74.11% for GDML and 67.18%-90.76% for GDMLD in static mode. Similarly, in pre-charge phase of dynamic mode, this value varies from 5.47%-28.22% for GDML and 14.55%-77.51% for GDMLD. For evaluation phase, average leakage power saving of 44.69%-74.11% for GDML and 67.18%-90.76% for GDMLD is achieved. Analysis of delay reveals that both the techniques increase delay of the design while providing significant leakage power saving.

该贡献提出了一种通过结合门控漏电晶体管（GLT）来降低双模逻辑（DML）电路中的泄漏功率的技术。产生的电路被命名为具有双模式逻辑（GDML）的GALEOR。此外，GDML设计通过包括脚形二极管晶体管而得到扩展，这样获得的设计被称为带脚形二极管双模逻辑的GALEOR（GDMLD）。使用有脚的A型和B型DML门进行分析，得到GDML和GDMLD变体，分别称为GDML-TA，GDML-TB，GDMLD-TA和GDMLD-TB。使用SymicaDE工具，使用两个输入NAND和NOR门以及一个全加法器和一个2位乘法器电路，以静态和动态模式研究90 nm和45 nm技术节点上的拟议技术。对泄漏功率的分析表明，其值随技术规模的增加而增加。在静态模式下，GDML的平均泄漏功率节省为44.69％-74.11％，GDMLD的平均泄漏功率节省为67.18％-90.76％。同样，在动态模式的预充电阶段，该值对于GDML为5.47％-28.22％，对于GDMLD为14.55％-77.51％。在评估阶段，GDML的平均泄漏功率节省为44.69％-74.11％，GDMLD的平均泄漏功率节省为67.18％-90.76％。延迟分析表明，这两种技术都增加了设计的延迟，同时显着节省了泄漏功率。