Memristor–CMOS (MCM) technology enables fabrication of thin film memristors over the conventional CMOS devices and has the potential to significantly reduce the silicon-area and propagation delays in VLSI chips. The memristor not only has an extremely very useful characteristic of non-volatile memory, but also has the advantage of significantly lesser ON resistance \(R_{on}\) and lesser undesired parasitic capacitance as compared to MOSFETs. Innovative MCM hybrid re-configurable circuits can outperform conventional CMOS-only design and hence are being considered as an important device for future digital VLSI applications. This paper presents applications of \({\mathrm{TiO}}_{2-x}\)–\({\mathrm{TiO}}_{2}\) memristor for digital multivibrator circuits at 45 nm CMOS technology node. The threshold adaptive memristor SPICE model has been used for design and performance-benchmarking of the proposed MCM multivibrators in circuit simulator (cadence^®) at 45 nm technology node. The proposed new MCM mono-stable vibrator has a delay of merely 16 ps (98% lower delay than similar CMOS design) and requires a 45% lesser silicon area. Similarly, the proposed new MCM bi-stable vibrator has a delay of merely 5 ps (87% lower delay than similar CMOS design) and requires a 25% lesser silicon area. Moreover, the proposed MCM mono-stable and bi-stable multivibrators consume merely 0.1 \(\upmu\)W and 0.5 \(\upmu\)W of power, respectively, as compared to the 0.47 \(\upmu\)W and 0.98 \(\upmu\)W power required by corresponding CMOS-only multi-vibrators. The overall decrease in power delay product is 99% and 94%, respectively, in the proposed MCM mono-stable and bi-stable multivibrators as compared to the corresponding conventional CMOS-only multivibrators.

忆阻器-CMOS（MCM）技术可以在常规CMOS器件上制造薄膜忆阻器，并具有显着减少VLSI芯片中的硅面积和传播延迟的潜力。与MOSFET相比，忆阻器不仅具有非常非常有用的非易失性存储器特性，而且还具有导通电阻\（R_on）\显着较小和寄生电容较小的优点。创新的MCM混合可重配置电路可以胜过传统的仅CMOS设计，因此被认为是未来数字VLSI应用的重要设备。本文介绍了\（{\ mathrm {TiO}} _ {2-x} \） – \（{\ mathrm {TiO}} _ {2} \）的应用用于45 nm CMOS技术节点的数字多谐振荡器电路的忆阻器。阈值自适应忆阻器SPICE模型已被用于设计和性能，在基准电路模拟器（韵律所提出的MCM多谐振荡器的^®在45纳米技术节点）。拟议中的新型MCM单稳态振子的延迟仅为16 ps（与类似的CMOS设计相比，延迟降低了98％），并且所需的硅面积减少了45％。类似地，提出的新型MCM双稳态振子的延迟仅为5 ps（与类似的CMOS设计相比，延迟降低了87％），并且所需的硅面积减少了25％。此外，与0.47相比，拟议的MCM单稳态和双稳态多谐振荡器分别仅消耗0.1 W （upmu） W和0.5 W （upmu） W的功率。\（\ upmu \） W和0.98 \（\ upmu \） W的功率，仅对应的CMOS多谐振荡器需要。与相应的仅使用CMOS的传统多谐振荡器相比，在建议的MCM单稳态和双稳态多谐振荡器中，功率延迟乘积的总体降低分别为99％和94％。