The main goal of this paper is to design an efficient 2D FIR digital filter for digital image processing and digital signal processing applications. To optimize filter speed, area and power different multipliers like array, Wallace tree, Booth and Vedic are used in the design of filters. Among these multipliers, Vedic multiplier reduces the partial products in multiplication. This increases the speed of the multiplication process. Vedic multiplier is based on ancient mathematics and uses a sutra called “Urdhva Tiryabhyam”. This paper, proposes two methods to optimize speed, area and power. The first method uses a predictor block in Vedic multiplier. This helps in predicting the outputs with the help of previous outputs. In the second method Reusable Logic blocks are used in Vedic multiplier. This method occupies only less number of LUTs and slice registers. The 2D FIR digital filter is designed and implemented using the two proposed multipliers and the state of art multipliers. The experimental results show that the 2D FIR digital filter using Vedic multiplier with predictor has 71.07% less EDP and using Vedic multiplier with Reusable Logic has 89.5% less EDP compared to conventional Vedic multiplier. The 2D FIR filter designed using Verilog HDL, synthesized, simulated and implemented using Xilinx FPGA. Comparison of simulation results show that 2D FIR filter implemented using the proposed methods optimizes the speed, area and power of the filter.

本文的主要目标是为数字图像处理和数字信号处理应用设计高效的2D FIR数字滤波器。为了优化滤波器速度，面积和功率，在滤波器设计中使用了不同的乘数，例如阵列，华莱士树，布斯和吠陀。在这些乘数中，吠陀乘数减少乘积中的部分乘积。这增加了乘法处理的速度。吠陀的乘数基于古老的数学原理，并使用一种名为“ Urdhva Tiryabhyam”的经文。本文提出了两种优化速度，面积和功率的方法。第一种方法使用吠陀乘法器中的预测器块。这有助于在先前输出的帮助下预测输出。在第二种方法中，吠陀乘法器中使用了可重用逻辑块。此方法仅占用较少的LUT和切片寄存器。2D FIR数字滤波器是使用两个建议的乘法器和最新的乘法器设计和实现的。实验结果表明，与传统的Vedic乘法器相比，使用带有预测器的Vedic乘法器的2D FIR数字滤波器的EDP减少了71.07％，而使用具有Reusable Logic的Vedic乘法器的EDP减少了89.5％。使用Verilog HDL设计的2D FIR滤波器，使用Xilinx FPGA进行合成，仿真和实现。仿真结果的比较表明，使用所提出的方法实现的二维FIR滤波器可优化滤波器的速度，面积和功率。实验结果表明，与传统的Vedic乘法器相比，使用带有预测器的Vedic乘法器的2D FIR数字滤波器的EDP减少了71.07％，而使用具有Reusable Logic的Vedic乘法器的EDP减少了89.5％。使用Verilog HDL设计的2D FIR滤波器，使用Xilinx FPGA进行合成，仿真和实现。仿真结果的比较表明，使用所提出的方法实现的二维FIR滤波器可优化滤波器的速度，面积和功率。实验结果表明，与传统的Vedic乘法器相比，使用带有预测器的Vedic乘法器的2D FIR数字滤波器的EDP减少了71.07％，而使用具有Reusable Logic的Vedic乘法器的EDP减少了89.5％。使用Verilog HDL设计的2D FIR滤波器，使用Xilinx FPGA进行合成，仿真和实现。仿真结果的比较表明，使用所提出的方法实现的二维FIR滤波器可优化滤波器的速度，面积和功率。