Approximate multipliers play vital role in the error-resilience applications by balancing accuracy and power efficiency. In this article, we improved the accuracy of approximate multipliers using a set of proposed approximate compressors which are able to compress any number of inputs to arbitrary numbers of output bits. To achieve better accuracy, probability of being one in the input bits is used to determine the compression ratio. Also, a novel scheme for allocating approximate and exact compressors in PPM is proposed to decrease column reduction stages. Error metrics namely P_E, MED, MRED, and NED are calculated to evaluate accuracy of our approximate compressors. Experimental results show an average of 35% accuracy improvement, in comparison with the previous approximate compressors. We implemented four different multipliers including 8-bit, 12-bit, 16-bit, and 24-bit multipliers to prove goodness of our proposed algorithm. The multipliers are designed by Verilog and synthesized in a 45-nm standard CMOS technology. The experimental results demonstrate major accuracy superiority of our proposed multipliers in comparison with the state of the art approximate multipliers in terms of MED, MRED, and NED. According to the experimental results, the delay is improved 22%, on average, compared with exact multipliers.

近似乘法器通过平衡精度和功率效率，在容错应用中起着至关重要的作用。在本文中，我们使用一组建议的近似压缩器提高了近似乘法器的精度，该压缩器能够将任意数量的输入压缩为任意数量的输出位。为了获得更好的精度，使用输入位中为1的概率来确定压缩率。此外，提出了一种在PPM中分配近似和精确压缩器的新颖方案，以减少列还原阶段。错误指标，即_PE，MED，MRED和NED进行计算，以评估我们近似压缩机的准确性。实验结果表明，与以前的近似压缩机相比，平均精度提高了35％。我们实现了四个不同的乘法器，包括8位，12位，16位和24位乘法器，以证明所提出算法的优越性。乘法器由Verilog设计，并以45纳米标准CMOS技术合成。实验结果表明，与MED，MRED和NED方面的最新近似乘法器相比，我们提出的乘法器在精度上有很大优势。根据实验结果，与精确乘法器相比，延迟平均提高了22％。