The system-on-chip (SoC) designs for future Internet of Things (IoT) systems, spanning client platforms to cloud datacenters, need to deliver uncompromising and scalable performance with extreme energy efficiency for diverse workloads and applications, while satisfying a wide range of energy budgets, as well as platform cooling and power delivery constraints. Low-latency, burst-mode responsiveness, and scalable high-throughput performance must be delivered on demand for a range of thread-parallel, task-parallel, and data-parallel workloads covering traditional and emerging applications. This article discusses the challenges and opportunities for many-core SoC design in scaled CMOS process operating over a wide voltage-frequency range including near-threshold-voltage (NTV) that can meet the compute demands of the future at scale, flexibly, and efficiently. This article covers: 1) circuit design techniques for NTV cores; 2) mitigation techniques for within-die parameter variations via multivoltage frequency schemes; 3) digital integrated voltage regulators (VRs) for fine-grain and wide-range voltage modulation; and 4) radiation-induced soft error rate (SER) characterization and mitigation techniques to enable reliable operation at NTV. Silicon prototype examples will be used to illustrate the different techniques and highlight future research directions.

中文翻译：

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规模化CMOS的大范围多核SoC设计：挑战与机遇

从客户端平台到云数据中心的未来物联网（IoT）系统的片上系统（SoC）设计，需要为各种工作负载和应用程序提供毫不妥协和可扩展的性能以及极高的能效，同时还要满足各种能源预算，以及平台冷却和电力输送的限制。必须针对涵盖传统和新兴应用程序的一系列线程并行，任务并行和数据并行工作负载，按需提供低延迟，突发模式响应能力和可扩展的高吞吐量性能。本文讨论了在宽电压-频率范围内运行的大规模CMOS工艺中的多核SoC设计所面临的挑战和机遇，该电压-频率范围可满足未来大规模，灵活地满足计算需求的近阈值电压（NTV），高效地 本文涵盖：1）NTV内核的电路设计技术；2）通过多电压频率方案的晶粒内参数变化的缓解技术；3）用于细粒度和宽范围电压调制的数字集成稳压器（VR）；和4）辐射诱发的软错误率（SER）表征和缓解技术，以实现NTV的可靠运行。硅原型示例将用于说明不同的技术并突出未来的研究方向。和4）辐射诱发的软错误率（SER）表征和缓解技术，以实现NTV的可靠运行。硅原型示例将用于说明不同的技术并突出未来的研究方向。和4）辐射诱发的软错误率（SER）表征和缓解技术，以实现NTV的可靠运行。硅原型示例将用于说明不同的技术并突出未来的研究方向。