Implementing wireline receivers with a front-end analog-to-digital converter (ADC) allows for complex, flexible, and robust signal processing algorithms in the digital domain, as well as easy implementation of advanced modulation schemes beyond binary PAM2. However, the power consumption of the ADC and ensuing digital equalization is a key issue for such receivers in high-speed applications. Embedding analog equalization inside the ADC architecture allows for both a lower ADC resolution and a reduced-complexity digital equalizer, resulting in a more power-efficient receiver. This article presents a 6-bit 1.5-GS/s time-interleaved successive approximation register (SAR) ADC with low-overhead two-tap embedded decision-feedback equalizer (DFE). A smart speculative DFE is proposed to reduce additional conversion cycles required for the equalization realization in the ADC. Moreover, DFE functions are efficiently embedded in the capacitive digital-to-analog converter (DAC) references. The prototype ADC with two-tap DFE is implemented in a 130-nm CMOS process and achieves a 5.24-bit peak effective number of bits and 0.59-pJ/conversion-step figure-of-merit (FOM) at a 1.5-GS/s sampling rate while consuming 34.1 mW and occupying a core area of 0.32 mm ² . The effectiveness of the embedded DFE in timing margin improvement is verified for 1.5-Gb/s operation over high-loss FR4 channels at a bit error rate (BER) of 10 ⁻⁹ .

中文翻译：

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具有130nm CMOS的智能投机性两分接头嵌入式DFE的6位1.5-GS / s SAR ADC，适用于有线接收器应用

使用前端模数转换器（ADC）来实现有线接收器，可以在数字域中实现复杂，灵活和强大的信号处理算法，并且可以轻松实现除二进制PAM2之外的高级调制方案。但是，对于此类高速应用中的接收器，ADC的功耗和随之而来的数字均衡是一个关键问题。在ADC体系结构中嵌入模拟均衡功能，既可以降低ADC分辨率，又可以降低复杂度的数字均衡器，从而实现更高能效的接收器。本文介绍了一种具有低开销两抽头嵌入式判决反馈均衡器（DFE）的6位1.5-GS / s时间交错的逐次逼近寄存器（SAR）ADC。提出了一种智能的推测性DFE，以减少ADC中实现均衡所需的额外转换周期。此外，DFE功能被有效地嵌入到电容式数模转换器（DAC）参考中。具有两抽头DFE的原型ADC在130 nm CMOS工艺中实现，在1.5-GS / G时实现了5.24位峰值有效位数和0.59 pJ /转换步长因数（FOM）。 s的采样率，同时消耗34.1 mW并占用0.32 mm的核心区域 ² 。对于高损耗FR4通道上1.5 Gb / s的操作，以10 ^-9的误码率（BER）验证了嵌入式DFE在时序裕度改善方面的有效性 。