As process geometries shrink below 45 nm, accurate and efficient gate-level timing analysis becomes even more challenging. Modern VLSI interconnects are more resistive, signals no longer resemble saturated ramps, and gate input pins exhibit a significant Miller effect. Over recent years, the semiconductor industry has adopted current source models (CSMs) for accurate gate modeling. Industrial gate models, however, are precharacterized assuming capacitive loads, which poses significant challenges to the approximation of the highly resistive load interconnect with an effective capacitance ( $\text{C} _{\text{eff}}$ ). In fact, most related works are either computationally expensive or unable to approximate the output slew. Furthermore, they require additional precharacterization and ignore the Miller effect. In this article, we present an iterative methodology for fast and accurate gate delay estimation. The proposed approach accurately computes the driver output waveform, using closed-form formulas to calculate a ${C} _{\text{eff}}$ per waveform segment, while accounting for their interdependence. Thus, it allows for variable analysis resolution exploiting an accuracy/runtime tradeoff. In contrast to prior works, our approach is compatible with conventional CSMs and considers the impact of Miller capacitance. We evaluate our method on representative driver-load test circuits consisting of interconnects with arbitrary $RC$ characteristics and ASU ASAP 7-nm standard cells. The proposed method achieves 1.3% and 2.5% delay and slew root-mean-square percentage error (RMSPE) against SPICE, respectively. In addition, it provides high efficiency, as it converges in 2.3 iterations on average.

中文翻译：

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具有库兼容电流源模型和有效电容的栅极延迟估计

随着工艺几何尺寸缩小到45 nm以下，准确，高效的门级时序分析变得更具挑战性。现代VLSI互连的电阻更大，信号不再类似于饱和斜坡，并且栅极输入引脚表现出显着的米勒效应。近年来，半导体行业已采用电流源模型（CSM）进行精确的栅极建模。但是，工业门模型的特征是假设电容性负载，这对具有有效电容的高阻负载互连的近似提出了巨大挑战（ $ \ text {C} _ {\ text {eff}} $ ）。实际上，大多数相关工作要么计算量大，要么无法估计输出摆率。此外，它们需要额外的预特征化，而忽略了米勒效应。在本文中，我们提出了一种用于快速，准确地进行门延迟估计的迭代方法。所提出的方法使用闭式公式来精确计算驱动器输出波形 $ {C} _ {\ text {eff}} $ 每个波形段，同时考​​虑它们的相互依赖性。因此，它允许利用准确性/运行时间权衡来进行变量分析分辨率。与以前的工作相比，我们的方法与常规CSM兼容，并考虑了米勒电容的影响。我们在由任意互连组成的代表性驱动器负载测试电路上评估我们的方法 $ RC $ 特性和ASU ASAP 7纳米标准单元。所提出的方法相对于SPICE分别实现了1.3％和2.5％的延迟以及均方根误差（RMSPE）。此外，它平均收敛2.3次迭代，因此具有很高的效率。