As basic components, optimizing power consumption of flip-flops (FFs) can significantly reduce the power of digital systems. In this article, an energy-efficient retentive true-single-phase-clocked (TSPC) FF is proposed. With the employment of input-aware precharge scheme, the proposed TSPC FF precharges only when necessary. In addition, floating node analysis and transistor level optimization are employed to further ensure the high energy efficiency of the FF without significantly increasing the area. Postlayout simulations based on SMIC 55-nm CMOS technology show that at a supply voltage of 1.2 V, the power consumption of the proposed FF is 84.37% lower than that of conventional transmission-gate flip-flop (TGFF) at 10% data activity. The reduction rate is increased to 98.53% as the data activity goes down to 0%. When the supply voltage decreases to 0.6 V, the proposed FF consumes only 0.411 fJ/cycle at 10% data activity, which is 84.23% lower than TGFF. Measurement results of ten test chips demonstrate the great energy efficiency of the proposed FF. Furthermore, the CK-to-Q delay of the proposed FF is 26.18% lower than that of TGFF at a supply voltage of 1.2 V.

中文翻译：

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具有免冗余预充电操作的低功耗保持性真正单相时钟触发器


作为基本组件，优化触发器（FF）的功耗可以显着降低数字系统的功耗。在本文中，提出了一种高能效保持性真单相时钟 (TSPC) FF。通过采用输入感知预充电方案，所提出的 TSPC FF 仅在必要时进行预充电。此外，采用浮动节点分析和晶体管级优化，在不大幅增加面积的情况下进一步保证FF的高能效。基于中芯国际 55 nm CMOS 技术的版图后仿真表明，在 1.2 V 电源电压下，在 10% 数据活动时，所提出的 FF 的功耗比传统传输门触发器 (TGFF) 低 84.37%。当数据活动降至 0% 时，减少率增加至 98.53%。当电源电压降低至 0.6 V 时，所提出的 FF 在 10% 数据活动下仅消耗 0.411 fJ/周期，比 TGFF 低 84.23%。十个测试芯片的测量结果证明了所提出的 FF 的巨大能源效率。此外，在电源电压为 1.2 V 时，所提出的 FF 的 CK-to-Q 延迟比 TGFF 低 26.18%。