Vertical transistors—in which the channel length is determined by the thickness of the semiconductor—are of interest in the development of next-generation electronic devices. However, short-channel vertical devices are difficult to fabricate, because the high-energy metallization process typically results in damage to the contact region. Here we show that molybdenum disulfide (MoS₂) vertical transistors with channel lengths down to one atomic layer can be created using a low-energy van der Waals metal integration technique. The approach uses prefabricated metal electrodes that are mechanically laminated and transferred on top of MoS₂/graphene vertical heterostructures, leading to vertical field-effect transistors with on–off ratios of 26 and 10³ for channel lengths of 0.65 nm and 3.60 nm, respectively. Using scanning tunnelling microscopy and low-temperature electrical measurements, we show that the improved electrical performance is the result of a high-quality metal–semiconductor interface, with minimized direct tunnelling current and Fermi-level pinning effect. The approach can also be extended to other layered materials (tungsten diselenide and tungsten disulfide), resulting in sub-3-nm p-type and n-type vertical transistors.

垂直晶体管——其中沟道长度由半导体的厚度决定——在下一代电子设备的开发中具有重要意义。然而，短沟道垂直器件难以制造，因为高能金属化工艺通常会损坏接触区。在这里，我们展示了可以使用低能范德华金属集成技术创建沟道长度低至一个原子层的二硫化钼 (MoS _{2 ) 垂直晶体管。}该方法使用预制金属电极，将其机械层压并转移到 MoS _{2 /石墨烯垂直异质结构之上，从而产生具有 26 和 10} ³开关比的垂直场效应晶体管通道长度分别为 0.65 nm 和 3.60 nm。使用扫描隧道显微镜和低温电学测量，我们表明改进的电性能是高质量金属-半导体界面的结果，具有最小化的直接隧道电流和费米能级钉扎效应。该方法还可以扩展到其他分层材料（二硒化钨和二硫化钨），从而产生亚 3 纳米的 p 型和 n 型垂直晶体管。