Testing of high-speed integrated circuits that enable 100-Gb Ethernet is a complex and expensive proposition. It becomes increasingly difficult to carry out measurements with probes if the test chip’s pad count is very high. A full-fledged packaging solution to test a chip requires a lot of resources and incurs a considerable cost. Other approaches, such as using flip-chip-on-board, prove to be expensive as well. On-board electrical interconnects, if appropriately designed, can be used with wire-bonded dies to perform high-speed measurements using ordinary methods. This article discusses the design and development of a platform to test a high-speed equalizer chip designed for the 100-Gb/s dual polarization-quadrature phase shift keying-based optical links. It also shows how careful optimization of the test platform addressing the aspects of signal delivery from connectors to chip pads through broadband transmission lines and bond-wire transitions and thermal management facilitates the use of low-cost methods to test high-performance chips. Detailed descriptions of the test platform and its validation using $S$ -parameter measurements and the experimental results with an optical system are also presented.

中文翻译：

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一种用于测试高性能集成电路的经济有效的解决方案

对支持100 Gb以太网的高速集成电路进行测试是一项复杂而昂贵的提议。如果测试芯片的焊盘数非常高，使用探针进行测量就变得越来越困难。用于测试芯片的完整封装解决方案需要大量资源，并且会产生可观的成本。其他方法，例如使用板上倒装芯片，也被证明是昂贵的。如果适当设计，板载电气互连可以与引线键合管芯一起使用，以使用常规方法执行高速测量。本文讨论了一个平台的设计和开发，该平台可以测试针对基于100 Gb / s双偏振正交相移键控的光链路设计的高速均衡器芯片。它还显示了对测试平台的精心优化，以解决通过宽带传输线和键合线过渡以及热管理从连接器到芯片焊盘的信号传输方面的问题，从而促进了低成本方法对高性能芯片的测试。测试平台及其使用验证的详细说明 $ S $ 还介绍了参数测量和光学系统的实验结果。