The gate-all-around nanowire FET (GAA NW FET) is one of the most promising architectures for the next generation of transistors as it provides better performance than current mass-produced FinFETs, but it has been proven to be strongly affected by variability. For this reason, it is essential to be able to characterize device performance which is done by extracting the figures of merit (FoM) using data from the IV curve. In this work, we use numerical simulations to evaluate the effect of the threshold voltage ( $\mathrm {V_{TH}}$ ) extraction method on the variability estimation for a gate-all-around nanowire FET. For that, we analyse the impact of four sources of variability: gate edge roughness (GER), line edge roughness (LER), metal grain granularity (MGG) and random discrete dopants (RDD). We have considered five different extraction methods: the second derivative (SD), constant current (CC), linear extrapolation (LE), third derivative (TD) and transconductance-to-current-ratio (TCR). For the ideal non-deformed device at high drain bias, the effect of the extraction technique can lead to a 137 mV difference in $\mathrm {V_{TH}}$ and an 89 mV/V difference in the drain-induced-barrier-lowering (DIBL), and when considering GER and LER variability, the influence of the extraction method leads to differences in the standard deviation values of the $\mathrm {V_{TH}}$ distribution ( $\sigma \mathrm {V_{TH}}$ ) of up to 2.3 and 3.7 mV respectively, values comparable to intrinsic parameter variations. Therefore, the $\mathrm {V_{TH}}$ extraction technique presents itself as an additional parameter that should be included in performance comparisons as it can heavily impact the results.

中文翻译：

---

阈值电压提取方法是否会影响器件的可变性？

环绕栅纳米线FET（GAA NW FET）是下一代晶体管最有前途的架构之一，因为它提供的性能要优于当前批量生产的FinFET，但事实证明，可变性会对它产生很大的影响。因此，至关重要的是能够表征器件性能，这是通过使用来自IV曲线的数据提取品质因数（FoM）来完成的。在这项工作中，我们使用数值模拟来评估阈值电压的影响（ $ \ mathrm {V_ {TH}} $ 绕栅纳米线FET变异性估算的提取方法）。为此，我们分析了四个可变性来源的影响：栅极边缘粗糙度（GER），线边缘粗糙度（LER），金属颗粒粒度（MGG）和随机离散掺杂剂（RDD）。我们考虑了五种不同的提取方法：二阶导数（SD），恒流（CC），线性外推（LE），三阶导数（TD）和跨导电流比（TCR）。对于理想的高漏极偏置的未变形器件，提取技术的效果可能会导致137 mV的压差。 $ \ mathrm {V_ {TH}} $ 漏极诱导势垒降低（DIBL）的差异为89 mV / V，考虑GER和LER的可变性时，提取方法的影响会导致漏极的标准差值的差异。 $ \ mathrm {V_ {TH}} $ 分配 （ $ \ sigma \ mathrm {V_ {TH}} $ 分别高达2.3 mV和3.7 mV的电压），其值可与固有参数变化相媲美。因此， $ \ mathrm {V_ {TH}} $ 提取技术将其自身作为附加参数，应该包含在性能比较中，因为它会严重影响结果。