In this paper, eight different SRAM cells are studied and evaluated with a 65nm CMOS technology. The cells were designed with radiation-hardening-by-design approaches including schematic and layout techniques. The eight types of cells were placed into eight pages of an SRAM test chip. The alpha and proton irradiation demonstrated that the Dual Interlocked Cell (DICE) has the best radiation-tolerant performance, but requires the largest area. The 6T and 11T cells designed with charge cancellation techniques can reduce soft errors up to 2-3 times with less area overhead. Several DICE variants were developed with reduced area overhead and showed SEU resilience performance equivalent to DICE. Simulation results are also presented in this paper to validate the findings.

在本文中，使用65nm CMOS技术研究和评估了八个不同的SRAM单元。电池采用辐射硬化设计方法进行设计，包括示意图和布局技术。八种类型的单元被放入SRAM测试芯片的八页中。α和质子辐射证明双重互锁单元（DICE）具有最佳的耐辐射性能，但需要最大的面积。采用电荷消除技术设计的6T和11T电池可将软错误减少多达2-3倍，而面积开销却更少。开发了几种DICE变体，减少了系统开销，并显示出与DICE相当的SEU弹性。本文还提供了仿真结果以验证发现。