VLSI is an enduring technology which is used to change the entire digital element into autonomy, some real-time opportunities are characterized under Very Large Scale Integration such as low power application, testing, MOS technology etc. This research focused on signal processing in low power VLSI design, in existing system the backend IC fabrication process illustrates system-level design by using digital logic elecment. An existing digital element consist of different functions of adders such as carry select, ripple carry adder, carry skip adder, carry look ahead adder, which has consume more area, delay, and power. To improve the efficiency of digital design a novel majority carry save adder is proposed and incorporate with a structured tree multiplier, this research produce an optimized carry save adder design in digital filter for improve the signal to noise ratio. The proposed innovative carry save adder is constructed by using majority logic and implemented into a digital FIR filter, this new technique consumes low power, delay-free carry circuit and less number of gate counts. The proposed adder has achieved 96 % efficiency in terms of gate count, delay, and power compared with existing analysis. Digital system design produces 83.5 % efficiencyin an existing system and it required the maximum number of gate count and an increasing number of delays when compared with recent research. The design summary is analyzed by using XILINX 14.7 ISE synthesis and the implementation process is highly reached with the help of MATLAB 2018a. The proposed design is implemented into Biomedical Application for reducing noise and improving signal to noise ratio.

VLSI是一项经久耐用的技术，用于将整个数字元素转变为自主性，在超大规模集成下，一些实时机会如低功耗应用，测试，MOS技术等得到了体现。这项研究的重点是低功耗信号处理VLSI设计，在现有系统中，后端IC的制造过程通过使用数字逻辑元件来说明系统级设计。现有的数字元件由加法器的不同功能组成，例如进位选择，纹波进位加法器，进位跳过加法器，进位前瞻加法器，这消耗了更多的面积，延迟和功率。为了提高数字设计的效率，提出了一种新颖的多数保留保存加法器，并将其与结构化树乘法器结合在一起，这项研究在数字滤波器中产生了一种优化的进位保存加法器设计，以提高信噪比。提出的创新进位保存加法器采用多数逻辑构建，并实现到数字FIR滤波器中，这项新技术消耗低功耗，无延迟的进位电路和较少的门数。与现有分析相比，拟议的加法器在门数，延迟和功率方面已实现96％的效率。数字系统设计在现有系统中可产生83.5％的效率，与最近的研究相比，它需要最大数量的门控数量和越来越多的延迟。使用XILINX 14.7 ISE综合分析了设计摘要，并借助MATLAB 2018a高度实现了实现过程。