Dopingless tunnel field effect transistor (DL-TFET) exhibits a great potential for lowering the sub-threshold current and hence increases the I_ON/I_OFF ratio because of its electrostatically doped source and drain. An analytical model for double gate dopingless tunnel field transistor (DG-DL TFET) is developed, for the first time, by calculating the source and drain work-function-induced doping and using it for solving the 2D Poisson’s equation in various regions. Electric potentials, energy band diagrams, electric field, corresponding drain current characteristics, and trans-conductance are obtained through the developed model and are validated by performing extensive device simulation for different gate and drain bias voltages. An excellent match between modeled and simulated results proves the efficacy of the developed model. The I_ON current obtained in Si-based dopingless TFET is 0.16 µA/µm, I_OFF has reduced to 0.296 fA/µm and I_ON/I_OFF obtained from the proposed device structure is 5.4 × 10⁸, and the sub-threshold swing is 50.77 mV/decade. The DG-DL TFET is analyzed for resistive load inverter characteristics and has been further investigated for realizing digital logic functions by controlling the gates of the device independently. The realization of NAND gate requires one “p-type DG-DL TFET”, whereas OR gate requires one “n-type DG-DL TFET”. The implementations of single bias-controlled logics are useful as they render energy-efficient operations and simultaneously increase the packaging density.

无掺杂隧道场效应晶体管 (DL-TFET) 显示出降低亚阈值电流的巨大潜力，因此增加了 I _ON /I _OFF由于其静电掺杂的源极和漏极的比率。首次建立了双栅无掺杂隧道场晶体管（DG-DL TFET）的分析模型，通过计算源漏功函数诱导的掺杂，并将其用于求解各个区域的二维泊松方程。通过开发的模型获得电势、能带图、电场、相应的漏极电流特性和跨导，并通过对不同的栅极和漏极偏置电压进行广泛的器件仿真来验证。建模和模拟结果之间的完美匹配证明了所开发模型的有效性。在 Si 基无掺杂 TFET 中获得的 I _{ON电流为 0.16 µA/µm，I OFF}已降低到 0.296 fA/µm 并且 I从所提出的器件结构获得的_ON /I _{OFF为 5.4 × 10} ⁸，亚阈值摆幅为 50.77 mV/decade。分析了 DG-DL TFET 的电阻负载逆变器特性，并进一步研究了通过独立控制器件的栅极来实现数字逻辑功能。NAND门的实现需要一个“p-type DG-DL TFET”，而OR门需要一个“n-type DG-DL TFET”。单偏压控制逻辑的实现很有用，因为它们可以实现节能操作并同时增加封装密度。