Reducing the number of visits to failure-free nodes can effectively reduce the reconstruction time of logical columns and improve the reconstruction efficiency. In this paper, we describe a new method to speed up the reconfiguration for the VLSI arrays. An efficient algorithm was proposed based on shortest path first principle for accelerating reconfiguration of VLSI processor subarrays with high power efficiency to meet the requirement of the power consumption of embedded system. The proposed algorithm greatly reduces the number of visits to the fault-free PEs for constructing a local optimal logical column and effectively reduces the construction time. Experimental results show that the proposed algorithm is capable of reducing the consumption time by 32.15% and reducing the numbers of visited PEs by 49.61% for a 128 × 128 host array with 20% falut rate.

减少无故障节点的访问次数可以有效减少逻辑列的重构时间，提高重构效率。在本文中，我们描述了一种加快VLSI阵列重新配置速度的新方法。提出了一种基于最短路径优先原则的高效算法，以加速高功率效率的VLSI处理器子阵列的重构，以满足嵌入式系统功耗的要求。所提出的算法大大减少了对无故障PE的访问次数，从而构建了局部最优逻辑列，有效地减少了构建时间。实验结果表明，该算法能够将消耗的时间减少32.15％，将访问的PE的数量减少49个。