We propose fast and efficient hardware architectures for a 2-D Bose-Chaudhuri-Hocquenghem (BCH) code of size n×n, with a quasi-cyclic burst error correction capability of t×t, in the frequency domain for data storage applications. A fully parallel encoder with the ability to produce an output every clock cycle was designed. Using conjugate class properties of finite fields, the algorithmic complexity of the encoder was significantly reduced, leading to a reduction in the number of gates by about 94% of the brute-force implementation per 2-D inverse discrete finite field Fourier transform (IDFFFT) point for a 15×15, t=2 2-D BCH code. We also designed a pipelined, low-latency decoder for the above encoder. The algorithmic complexity of various pipeline stages of the decoder was reduced significantly using finite field properties, reducing the space complexity of the entire decoder. For a particular case of n=15 and t=2, the architectures were implemented on a Kintex 7 KC-705 field-programmable gate array (FPGA) kit, giving high throughputs of 22.5 and 5.6 Gb/s at 100 MHz for the encoder and decoder, respectively.

中文翻译：

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用于二维数据存储应用的频域二维 BCH 码的高效硬件架构


我们为大小为 n×n 的 2-D Bose-Chaudhuri-Hocquenghem (BCH) 码提出了快速高效的硬件架构，在数据存储应用的频域中具有 t×t 的准循环突发纠错能力。设计了一种完全并行的编码器，能够在每个时钟周期产生输出。利用有限域的共轭类属性，编码器的算法复杂度显着降低，从而使每个二维离散有限域傅里叶逆变换 (IDFFFT) 的强力实现的门数减少了约 94% 15×15、t=2 2-D BCH 码的点。我们还为上述编码器设计了一个流水线、低延迟的解码器。利用有限域属性显着降低了解码器各个流水线阶段的算法复杂度，从而降低了整个解码器的空间复杂度。对于 n=15 和 t=2 的特定情况，该架构在 Kintex 7 KC-705 现场可编程门阵列 (FPGA) 套件上实现，为编码器提供 100 MHz 下 22.5 和 5.6 Gb/s 的高吞吐量和解码器，分别。