Emerging computation-in-memory (CIM) paradigm offers processing and storage of data at the same physical location, thus alleviating critical memory-processor communication bottlenecks suffered by conventional von-Neumann architecture. Storage of data in a CIM architecture is analog in nature and therefore computation is performed in analog domain i.e. inputs and outputs are analog values. Since the outside computing environment is digital, analog-to-digital converters (ADC) are utilized to perform the output data conversion. However, ADC designs are bulky, power-hungry circuits that are prone to design variations and therefore, play an important role in determining the computing efficiency of CIM architectures. In this paper, we present a scalable and reliable integrate and fire circuit ADC (SRIF-ADC) design for CIM architectures, suitable for stringent power and area constraints. We devise a technique to stabilize the node receiving analog inputs that allows more rows to be activated at the same time, thereby increasing the operand size of input vectors. This allows better scalability in terms of higher parallelism of operations. We employ a self-timed variation-aware design approach and design measures to drastically reduce read disturb of memristor devices that address reliability issues related to the ADC design. In addition, we present a compact, built-in sample-and-hold circuit to replace the large-sized capacitance and built-in weighting technique to alleviate the need for post-processing. For multiply-and-accumulate (MAC) operation, our simulation results show that we can improve the computational parallelism by 3X as well as ADC conversion speed and energy efficiency are improved by 2X and 11.6X, respectively, compared to the state-of-the-art design.

中文翻译：

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SRIF：适用于基于忆阻器的CIM架构的可扩展且可靠的集成和发射电路ADC

新兴的 内存计算（CIM）范式可在同一物理位置提供数据的处理和存储，从而减轻了传统von-Neumann架构遭受的关键内存-处理器通信瓶颈。CIM体系结构中的数据存储本质上是模拟的，因此计算是在模拟域中进行的IE输入和输出是模拟值。由于外部计算环境是数字的，模数转换器（ADC）用于执行输出数据转换。但是，ADC设计是体积庞大，耗电大的电路，容易发生设计变化，因此在确定CIM架构的计算效率方面起着重要作用。在本文中，我们提出了一个可扩展，可靠的集成和触发电路适用于CIM架构的ADC（SRIF-ADC）设计，适用于严格的功率和面积限制。我们设计了一种稳定接收模拟输入的节点的技术，该技术允许同时激活更多行，从而增加输入向量的操作数大小。就更高的操作并行性而言，这允许更好的可伸缩性。我们采用自定时变化感知设计方法和设计措施，以大幅度减少忆阻器器件的读取干扰，从而解决与ADC设计相关的可靠性问题。此外，我们提出了一种紧凑的内置采样保持电路，以取代大容量电容和内置加权技术，从而减轻了对后处理的需求。为了乘积 （MAC）操作，我们的仿真结果表明，与最新设计相比，我们可以将计算并行度提高3倍，并且ADC转换速度和能效分别提高2倍和11.6倍。