Dynamic power is a major source of power dissipation for high speed designs. Domain isolation methodology is a recently-proposed technique for reducing dynamic power based on controlling the evaluation phase of dynamic logic (toggling control). This work demonstrates some design issues in the domain isolation methodology and explains why it is inefficient with pipelined systems. We propose fixes for its identified issues, which enables using the toggling control with pipelined systems in a more efficient way. A novel flow named “Power Reduction Flow” is proposed for reducing dynamic power of digital circuits. Our flow uses novel design analytical methods, novel “Dynamic Logic Modifier Flow”, and novel “Dynmic Logic Area Validation Flow” for reducing dynamic power with conditionally improving performance. The new design analytical methods are based on probability theory, SystemVerilog covergroups, and digital circuit modeling. A new event type perspective is also proposed to analyze designs to reduce dynamic power in them. Experimental results using TSMC 65 nm and low supply voltages show up to 59% power reduction compared to the original traditional techniques with improving circuit’s performance by $3\times $ of its original maximum operating frequency at the cost of an extra 12.3% increase in area.

中文翻译：

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减少动态功率和改善条件性能的新流程

动态功率是高速设计功耗的主要来源。域隔离方法是一种最近提出的技术，用于基于控制动态逻辑的评估阶段（切换控制）来降低动态功耗。这项工作演示了域隔离方法中的一些设计问题，并解释了为什么它在流水线系统中效率低下。我们提出了针对已发现问题的修复程序，从而可以更有效地将切换控件与流水线系统一起使用。为了减少数字电路的动态功率，提出了一种名为“功率降低流”的新颖流程。我们的流程使用新颖的设计分析方法，新颖的“动态逻辑修改器流程”和新颖的“动态逻辑区域验证流程”来减少动态功耗并有条件地改善性能。新的设计分析方法基于概率论，SystemVerilog覆盖组和数字电路建模。还提出了一种新的事件类型视角来分析设计，以减少设计中的动态功耗。使用台积电65纳米和低电源电压的实验结果表明，与原始传统技术相比，功率降低了59％，可通过改善电路性能来实现 $ 3 \次$ 原来的最大工作频率，但面积增加了12.3％。