Beyond 5G systems are expected to approach 1 Tb/s throughput. This poses a significant challenge to the channel decoder. In this paper, we propose a multi-core architecture based on full row parallel layered LDPC decoder with frame interleaving. Compared with conventional partially parallel layered architectures, the proposed architecture increases the throughput by applying frame interleaving into the pipeline architecture and by using multi-core architectures. Two high rate medium size QC LDPC codes are designed with fast decoding convergence speed for this architecture. Both codes are implemented with single core and multi-core architectures to explore different trade-offs between code design, communication performance and implementation. The four decoders are implemented in 16 nm CMOS FinFET technology with a clock rate of 1 GHz. The placement and routing implementation results show that the single core decoder for the LDPC (1027, 856) code is able to provide 114 Gb/s throughput at maximum 3 iterations with an area of 0.173 mm ² and energy efficiency of 1.56 pJ/bit; the multi-core decoder for the (1032, 860) code is able to provide 860 Gb/s throughput at maximum 2 iterations with an area of 1.48 mm ² and energy efficiency of 3.24 pJ/bit. The multi-core decoder achieves the highest throughput in the literature for medium size (1–2k) LDPC codes. When compared with other state-of-the-art fully parallel high speed architectures, the proposed architectures bring a significant gain both in area efficiency and energy efficiency while keeping the ability to offer flexibility in code rate, number of iterations and early stop.

中文翻译：

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高速LDPC解码器达到1 Tb / s

超越5G的系统预计将达到1 Tb / s的吞吐量。这对信道解码器构成了重大挑战。在本文中，我们提出了一种基于具有帧交织的全行并行分层LDPC解码器的多核体系结构。与传统的部分并行分层体系结构相比，该提议的体系结构通过将帧交织应用于流水线体系结构并使用多核体系结构，从而提高了吞吐量。针对此架构，设计了两种具有中等解码速度的高速率QC LDPC码，它们具有快速的解码收敛速度。两种代码都采用单核和多核体系结构实现，以探索代码设计，通信性能和实现之间的不同权衡。四个解码器采用16 nm CMOS FinFET技术实现，时钟速率为1 GHz。 ²，能量效率为1.56 pJ / bit；（1032，860）代码的多核解码器能够以最大的2次迭代提供860 Gb / s的吞吐量，面积为1.48 mm ²，能效为3.24 pJ / bit。对于中等大小（1-2k）的LDPC码，多核解码器实现了文献中最高的吞吐量。与其他现有技术的全并行高速架构相比，拟议的架构在面积效率和能效方面均获得了显着提高，同时保持了在编码率，迭代次数和提前停止方面提供灵活性的能力。