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Time-Gated and Multi-Junction SPADs in Standard 65 nm CMOS Technology
IEEE Sensors Journal ( IF 4.3 ) Pub Date : 2021-03-02 , DOI: 10.1109/jsen.2021.3063319
Wei Jiang , Yamn Chalich , Ryan Scott , M. Jamal Deen

SPADs (Single-Photon Avalanche Diodes) are important detectors for a wide range of applications including positron emission tomography, Raman spectroscopy, light detection and ranging, and quantum key distribution. For some applications, custom image sensor technologies are used, but at a higher cost and lower performance imagers when compared to implementation in a standard planar CMOS technology. In this paper, we explore time-gating and multi-junction techniques to improve the SPAD’s performance in smaller standard planar CMOS processes to take advantage of their potential for monolithic integration with other advanced, mixed-signal circuitry for simple, low-cost, high-performance imaging solutions. A passively quenched, unbuffered, triple-junction SPAD structure was designed in a standard 65 nm CMOS process from TSMC. The characterization of the SPAD junctions in this process is the first in literature and proves useful for SPAD designers aiming for advanced CMOS technology nodes. The time-gated (TG) pixel design used the top shallow junction. The potential for improved photon detection efficiency and wavelength distinction through a multi-junction design was investigated. Our testing demonstrated that the proposed implementation of the triple-junction SPAD in this technology node is not suitable for wavelength distinction. The TG design achieved a fill-factor of 28.6%, and at an excess voltage of 300 mV, it achieved a peak photon detection efficiency of ~2.1% at 440 nm, <1% afterpulsing probability for hold-off times >22 ns, and <200 ps timing jitter.

中文翻译:

采用标准65 nm CMOS技术的时控和多结SPAD

SPAD(单光子雪崩二极管)是广泛应用中的重要探测器,包括正电子发射断层扫描,拉曼光谱,光检测和测距以及量子密钥分配。对于某些应用,使用了自定义图像传感器技术,但是与标准平面CMOS技术中的实现方式相比,其成本更高且性能更低。在本文中,我们探索时间门控和多结技术,以提高SPAD在较小的标准平面CMOS工艺中的性能,以利用其与其他先进的混合信号电路进行单片集成的潜力,从而实现简单,低成本,高集成度性能成像解决方案。台积电采用标准的65 nm CMOS工艺设计了被动淬火,无缓冲的三结点SPAD结构。在此过程中,SPAD结的特性描述是文献中的第一篇,并且证明对瞄准高级CMOS技术节点的SPAD设计人员很有用。时间门控(TG)像素设计使用顶部浅结。研究了通过多结设计提高光子检测效率和波长区分的潜力。我们的测试表明,在此技术节点中建议的三结点SPAD实现不适合波长区分。TG设计达到28.6%的填充因子,并且在300 mV的过电压下,在440 nm处实现了约2.1%的峰值光子检测效率,对于> 22 ns的保持时间,后脉冲概率小于1%,和<200 ps的定时抖动。
更新日期:2021-04-20
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