Conventional CMOS has become successful logic for most digital VLSI circuits and a good candidate in terms of power dissipation. But due to its dual nature, more transistors are required and are not suitable as the technology is scaled down. This paper proposes a Double Gate (DG) FinFET based 4-1, 8-1, 16-1 multiplexer (DFMs) with a reduced number of transistors catering to the needs of low-power dissipation and high speed. For designing the proposed 4-1 DG-FinFET digital multiplexer (DFM) circuit requires only 16 FinFETs. Compared to the CMOS multiplexer circuit's conventional architecture, the proposed 4-1 DFM design uses a single pull-up FinFET in its first stage, and the second stage has only 4 FinFETs. The DFM circuit design is extended to 8-1 and 16-1 targeting to reduce transistor count, delay, and power dissipation. Extensive simulations are done at a 22 nm technology node using Eldo software of Mentor Graphics. With the simulated results of proposed and conventional CMOS designs at different supply voltages and load capacitances on the 22 nm technology node, the proposed DFM multiplexers' power-delay product is better. For 1 GHz of frequency and the least feasible supply voltage of 0.8 V, the proposed digital multiplexer attains a 10% reduction in power dissipation and a 6% reduction in delay. Including inverters in the designs, the transistor count is also less compared to the conventional static multiplexer.

常规CMOS已成为大多数数字VLSI电路的成功逻辑，并且在功耗方面也很合适。但是由于其双重性质，随着技术的缩小，需要更多的晶体管，因此不适合使用。本文提出了一种基于4-1、8-1、16-1多路复用器（DFM）的双门（DG）FinFET，该晶体管具有数量减少的晶体管，可满足低功耗和高速的需求。为了设计建议的4-1 DG-FinFET数字多路复用器（DFM）电路，仅需要16个FinFET。与CMOS多路复用器电路的常规体系结构相比，建议的4-1 DFM设计在其第一阶段使用单个上拉FinFET，而第二阶段仅具有4个FinFET。DFM电路设计针对8-1和16-1进行了扩展，以减少晶体管数量，延迟和功耗。使用Mentor Graphics的Eldo软件在22 nm技术节点上进行了广泛的仿真。利用22 nm技术节点上不同电源电压和负载电容下拟议和常规CMOS设计的仿真结果，拟议DFM多路复用器的功率延迟乘积更好。对于1 GHz的频率和0.8 V的最小可行电源电压，建议的数字多路复用器的功耗降低了10％，延迟降低了6％。在设计中包括反相器，与传统的静态多路复用器相比，晶体管的数量也更少。建议的DFM多路复用器的功率延迟产品更好。对于1 GHz的频率和0.8 V的最小可行电源电压，建议的数字多路复用器的功耗降低了10％，延迟降低了6％。在设计中包括反相器，与传统的静态多路复用器相比，晶体管的数量也更少。建议的DFM多路复用器的功率延迟产品更好。对于1 GHz的频率和0.8 V的最小可行电源电压，建议的数字多路复用器的功耗降低了10％，延迟降低了6％。在设计中包括反相器，与传统的静态多路复用器相比，晶体管的数量也更少。