High leakage power consumption has become a serious problem in modern IC design. By isolating a block of circuit which is not in use from power supply, power gating has become one of the most effective ways to reduce leakage power. During the circuit wake-up process, turning on sleep transistors simultaneously may induce excessive surge current, which will threaten signal integrity. To avoid significant surge current, sleep transistor wake-up sequence should be carefully designed. On the other hand, PMOS sleep transistors may suffer from Negative-Bias Temperature Instability (NBTI) effect, and the wake-up time is increased after circuit aging. Conventional fixed wake-up sequence-based methods do not consider the NBTI effect, which may result in longer or unacceptable wake-up time after circuit aging. Therefore, in this paper, we propose a novel reconfigurable circuit structure that can reconfigure the wake-up sequence and a novel NBTI-aware wake-up strategy to reduce the wake-up time. Our strategy first finds a set of proper wake-up sequences under different aging circumstance and then dynamically reconfigures wake-up sequences at runtime based on the actual aging scenario (i.e. different months or years of aging). Experimental results show that compared with a traditional fixed wake-up sequence approach, our strategy can reduce up to 49.78% average wake-up time latency. Meantime, according to our estimation, to implement the reconfigurable wake-up sequence structure, the parasitic area overhead is only about 0.27% with a larger benchmark.

高泄漏功耗已成为现代IC设计中的一个严重问题。通过将不使用的电路块与电源隔离，电源门控已成为减少泄漏功率的最有效方法之一。在电路唤醒过程中，同时导通睡眠晶体管可能会引起过大的浪涌电流，这将威胁信号的完整性。为了避免产生较大的浪涌电流，应仔细设计睡眠晶体管唤醒序列。另一方面，PMOS睡眠晶体管可能会遭受负偏压温度不稳定性（NBTI）的影响，并且在电路老化后唤醒时间会增加。传统的基于固定唤醒序列的方法没有考虑NBTI效应，这可能导致电路老化后更长或更长时间的唤醒时间。因此，在本文中，我们提出了一种新颖的可重配置电路结构，它可以重新配置唤醒序列，以及一种新颖的NBTI感知唤醒策略，可以减少唤醒时间。我们的策略首先在不同的老化情况下找到一组合适的唤醒序列，然后根据实际老化情况（即不同的月份或年份）在运行时动态重新配置唤醒序列。实验结果表明，与传统的固定唤醒序列方法相比，我们的策略可以减少高达49.78％的平均唤醒时间延迟。同时，根据我们的估计，要实现可重构的唤醒序列结构，在具有较大基准的情况下，寄生面积开销仅为0.27％左右。