An ultra-low power ($3.9\text{nW}$), low supply-voltage ($0.6\text{V}$) and fully-tunable Gaussian-Bump circuit architecture for hardware-friendly implementation of Kernel functions is presented. The proposed architecture can be used to form hidden neuron cells for analog implementation of Radial Basis Functions in Neural Networks. It consists of only eleven transistors, all operating in sub-threshold. The Gaussian’s center, height and width are independently and electronically controlled. The proposed architecture is used as a building block to construct a 2-D Gaussian cascaded Bump structure, demonstrating its dimensional scalability. Proper operation, sensitivity and accuracy are confirmed via theoretical analysis and post-layout simulation results. The presented architectures were realized in TSMC $90\text{nm}$ CMOS process and were simulated using the Cadence IC Suite.

超低功耗（$3.9\text{净重}$），低电源电压（$0.6\text{伏特}$），并提出了用于硬件友好实现内核功能的完全可调的高斯凹凸电路架构。所提出的体系结构可用于形成隐藏的神经元细胞，以在神经网络中模拟径向基函数。它仅由十一个晶体管组成，所有晶体管均处于亚阈值以下。高斯的中心，高度和宽度是独立控制的，并通过电子方式控制。拟议的体系结构用作构建2维高斯级联凹凸结构的基础，证明了其尺寸可伸缩性。通过理论分析和布局后的仿真结果，可以确认正确的操作，灵敏度和准确性。所展示的架构是在台积电中实现的$90\text{纳米}$ CMOS工艺，并使用Cadence IC Suite进行了仿真。