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Advanced low damage manufacturing processes to fabricate SOI FinFETs and measurement of electrical properties
Microelectronics Reliability ( IF 1.6 ) Pub Date : 2021-04-15 , DOI: 10.1016/j.microrel.2021.114115
Ashish Kumar , Wen Hsi Lee , Y.L. Wang

In this paper, FinFETs are realized by integrating neutral beam etching(NBE) and microwave annealing (MWA) into the fabrication process. Electrical characteristics are measured at room temperature and parameters such as Sub-threshold swing of 89 mV/decade, Ion/Ioff of 106, DIBL of 72 mV/V and effective mobility (μeff) of 502 cm2V−1 s−1 are obtained with Wfin/Lgate = 40/100 nm. These characteristics are superior by using neutral beam etching than by using RIE-like condition, and the Vt shift at reduced Lgate is also suppressed. A damaged layer at high-k/Si interface by RIE-like condition is observed in the TEM image, which can correspond to the degradation in electrical characteristics. Furthermore, the proportional scaling of Ion versus Wfin indicates negligible S/D resistance due to good activation by Microwave annealing (MWA). In short, functional FinFETs were fabricated by Neutral beam etching (NBE) and Microwave annealing (MWA) for the first time, and these results pave ways for the techniques to be adopted in the advanced semiconductor processing. The SOI FinFETs demonstrate proportional scaling of on current versus the fin width and indicating that the S/D region is well activated by the microwave annealing method.



中文翻译:

先进的低损伤制造工艺,可制造SOI FinFET和测量电性能

本文通过将中性束刻蚀(NBE)和微波退火(MWA)集成到制造过程中来实现FinFET。电特性是在室温下和参数,例如89毫伏/十倍的亚阈值摆幅测量,我/ I的10 6,72毫伏/ V的DIBL和有效迁移率(μ EFF 502厘米)2 V -1通过W fin / L gate  = 40 / 100nm获得 s -1。与使用类似RIE的条件相比,使用中性束蚀刻具有更好的特性,而且在降低L栅极时V t漂移也被抑制了。在TEM图像中观察到了类似RIE条件的高k / Si界面处的损伤层,这可能与电特性的下降相对应。此外,由于微波退火(MWA)的良好激活,I on与W fin的比例缩放表明S / D电阻可忽略不计。简而言之,功能性FinFET是通过中性束蚀刻(NBE)和微波退火(MWA)首次制造的,这些结果为先进的半导体工艺中采用的技术铺平了道路。SOI FinFET展示了导通电流与鳍片宽度的比例关系,并表明通过微波退火方法可以很好地激活S / D区域。

更新日期:2021-04-16
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