The major design parameters of embedded cache memory (SRAM memory cell) are speed, power consumption, noise tolerance, and reliability. It is a challenging task to design an SRAM cell in the face of process, voltage, and temperature variations at low supply voltages. At scaled technology node the conventional 6T SRAM cell suffers from read and write failures as well as instability. Moreover, it is susceptible to multibit soft error rate since it does not support bit-interleaving architecture. This paper proposes a low-power robust single bitline 9T (nine transistor) SRAM (Static Random Access Memory) at a 16-nm technology node in the subthreshold region. The potency of the proposed cell is shown by comparing it with other recently published SRAM cells, namely, single-ended NTV 9T (SENTV9T), write and read enhanced 9T (WREN9T), and the conventional 6T (CONV6T) SRAM cells. The proposed cell provides 1.25×/1.96 × lower read current I_READ variability compared with WREN9T/SENTV9T. The proposed cell achieves 4.23 × higher noise tolerance capability (i.e., read static noise margin (RSNM)) during read operation compared with CONV6T due to the fact that it employs read decoupled operation. Moreover, SBL9T consumes lower standby power during hold state and dynamic power in the active state as compared with SENTV9T, WREN9T, and CONV6T. SBL9T also exhibits 10.01×/8.65×/11.47× narrower spread in standby power compared with CONV6T/WREN9T/SENTV9T. The dynamic power spread shows a similar trend with SBL9T providing 1.97×/1.02× narrower spread in dynamic power compared with WREN9T/SENTV9T. These benefits however are achieved by the SBL9T at the cost of 1.28×/0.71×/1.01× longer read delay compared with CONV6T/WREN9T/SENTV9T.

嵌入式高速缓存存储器（SRAM存储单元）的主要设计参数是速度，功耗，噪声容限和可靠性。面对低电源电压下的工艺，电压和温度变化，设计SRAM单元是一项艰巨的任务。在规模化的技术节点上，传统的6T SRAM单元遭受读取和写入失败以及不稳定的困扰。此外，由于它不支持位交织架构，因此容易受到多位软错误率的影响。本文在亚阈值区域的16nm技术节点处提出了一种低功耗，坚固的单位线9T（九晶体管）SRAM（静态随机存取存储器）。通过将建议的单元与最近发布的其他SRAM单元（即单端NTV 9T（SENTV9T），读写增强型9T（WREN9T））进行比较，可以显示该单元的效能。以及传统的6T（CONV6T）SRAM单元。拟议的单元提供1.25×/ 1.96×较低的读取电流I与WREN9T / SENTV9T相比，_读变异性大。与CONV6T相比，拟议的单元在读取操作期间实现了4.23×更高的噪声容忍能力（即读取静态噪声容限（RSNM）），这是因为它采用了读取解耦操作。此外，与SENTV9T，WREN9T和CONV6T相比，SBL9T在保持状态期间消耗的待机功率较低，而在活动状态下消耗的动态功耗更低。与CONV6T / WREN9T / SENTV9T相比，SBL9T的待机功耗分布也更窄10.01×/ 8.65×/ 11.47×。与WREN9T / SENTV9T相比，SBL9T的动态功率分布表现出相似的趋势，SBL9T的动态功率分布范围缩小了1.97倍/1.02倍。但是，与CONV6T / WREN9T / SENTV9T相比，SBL9T可以以更长的1.28×/ 0.71×/ 1.01×的读取延迟实现这些优势。