The performance and reliability enhancement achieved in a conventional double-gate (DG) junctionless field-effect transistor (JLFET) by introducing a vacuum gate dielectric towards the drain terminal and a high-\(\kappa\) gate dielectric (TiO\(_{2}\)) towards the source terminal is investigated. This arrangement of gate dielectrics enables enhanced gate controllability and offers significant protection against channel hot-carrier (CHC) effects at both device and circuit levels. At the device level, the DG-JLFET exhibits a 38% degradation in the drain current due to CHC stress, whereas the vacuum-gate DG-JLFET experiences only one-third of this value. The circuit-level analysis considers three benchmark circuits: ring oscillator (RO), static random-access memory (SRAM) cell, and common-source (CS) amplifier. The oscillating frequency of the RO is improved by 60% with the vacuum gate dielectric, with a 148% lower degradation in performance due to the CHC effect. The proposed approach is thus effective at both levels, not only improving the performance but also significantly enhancing the reliability.

在传统的双栅极（DG）无结场效应晶体管（JLFET）中，通过向漏极端子引入真空栅极电介质和高\（\ kappa \）栅极电介质（TiO \（_ {2} \））朝向源终端进行了调查。栅极电介质的这种布置可增强栅极的可控性，并在器件和电路级均提供显着的保护，以防止沟道热载流子（CHC）效应。在器件级别，由于CHC应力，DG-JLFET的漏极电流降低了38％，而真空门DG-JLFET的损耗仅为该值的三分之一。电路级分析考虑了三个基准电路：环形振荡器（RO），静态随机存取存储器（SRAM）单元和共源（CS）放大器。利用真空栅极电介质，RO的振荡频率提高了60％，由于CHC效应，性能降低了148％。因此，建议的方法在两个层面上都是有效的，