ABSTRACT

Ternary logic emerges as an alternative to the conventional binary logic in designing high performance, energy-efficient VLSI circuits because it reduces the number of interconnects and chip area. In this paper, we presented low power and high speed 9:2 encoder and 2:9 decoder designs based on ternary logic using carbon nanotube field effect transistors (CNTFETs). These circuits have been extensively simulated at 32 nm CNTFET technology at 0.9 V power supply voltage. The ternary decoder has a power delay product (PDP) of 24.62 aJ and the ternary encoder has a PDP of 133 aJ for a given load. In the proposed designs, the chirality of the carbon nanotube (CNT) is varied to control the threshold voltage. The designs have been analysed with process, voltage and temperature (PVT) variations and it is shown that with PVT variations the performance of the designs vary marginally.

摘要

在设计高性能、节能的 VLSI 电路时，三进制逻辑作为传统二进制逻辑的替代品出现，因为它减少了互连的数量和芯片面积。在本文中，我们介绍了使用碳纳米管场效应晶体管 (CNTFET) 基于三进制逻辑的低功耗和高速 9:2 编码器和 2:9 解码器设计。这些电路已在 0.9 V 电源电压下以 32 nm CNTFET 技术进行了广泛仿真。对于给定负载，三进制解码器的功率延迟积 (PDP) 为 24.62 aJ，而三进制编码器的 PDP 为 133 aJ。在所提出的设计中，改变碳纳米管 (CNT) 的手性以控制阈值电压。设计已经过过程分析，