ABSTRACT

This paper presents improved multiplexer-based ultra-low-power ternary Half Adder (HA), ternary Full Adder (FA), and ternary 1-bit multiplier designs. The proposed circuits consume 61–91% lesser power and can be implemented with 10–40% lesser number of transistors, as compared to the other corresponding circuits available in the literature. The reduction in power and transistor count has been achieved through improved multiplexer designs and judicious use of pass transistor logic. CNFETs have low gate capacitance and hence are ideal devices for ultra-low-power VLSI applications; however, CMOS technology is presently the most preferred technology, because of the easy and low-cost fabrication option made available by the well-established CMOS fabrication labs. Keeping this in view, the proposed mux-based ternary half adder has been designed with both 45 nm MOSFETs and CNFETs. The performance of the proposed HA design has been benchmarked with other CNFET HA reported in the literature. The proposed mux-based CNFET ternary HA, FA and 1-bit multiplier have 10–30% lesser propagation delays than the other designs available in the literature. The reduction in the Power Delay Product (PDP) is 85–99% in the proposed mux-based CNFET ternary circuits as compared to the other benchmarked designs.

摘要

本文介绍了改进的基于多路复用器的超低功耗三进制半加法器 (HA)、三进制全加器 (FA) 和三进制 1 位乘法器设计。与文献中可用的其他相应电路相比，所提出的电路消耗的功率减少了 61-91%，并且可以用减少 10-40% 的晶体管数量来实现。功率和晶体管数量的减少是通过改进多路复用器设计和明智地使用传输晶体管逻辑来实现的。CNFET 具有低栅极电容，因此是超低功耗 VLSI 应用的理想器件；然而，CMOS 技术是目前最受青睐的技术，因为成熟的 CMOS 制造实验室提供了简单且低成本的制造选择。考虑到这一点，所提议的基于多路复用器的三进制半加法器采用 45 nm MOSFET 和 CNFET 设计。所提出的 HA 设计的性能已与文献中报道的其他 CNFET HA 进行了基准测试。所提出的基于多路复用器的 CNFET 三元 HA、FA 和 1 位乘法器的传播延迟比文献中可用的其他设计少 10-30%。与其他基准设计相比，所提出的基于多路复用器的 CNFET 三元电路的功率延迟积 (PDP) 降低了 85-99%。