Three-Independent-Gate Field-Effect Transistors (TIGFETs) are a promising alternative technology that aims to replace or complement CMOS at advanced technology nodes. In this paper, we extracted the parasitic and intrinsic capacitances of a silicon-nanowire TIGFET device using three-dimensional numerical simulations in an attempt to accurately compare its capacitances and, consequently, circuit-level performances to CMOS at comparable nodes. Analytical models of the parasitic capacitances of a TIGFET transistor were derived using techniques such as the equivalent Schwarz-Christoffel transformation and standard cylindrical capacitors and show close agreement with numerical simulations. The maximum capacitance of a TIGFET transistor is 2× larger than for a 15 nm CMOS High Performance (HP) device due to the TIGFET's two additional gated contacts, but this is countered by its ability for multiple modes of operation which reduces the effective switching capacitance per device. A TIGFET transistor sees, on average, only a 30% increase in total capacitance compared to a CMOS HP device. Additionally, the TIGFET's increased device functionality can be used to modify the circuit-level architecture of a TIGFET-based design to mitigate the performance impact of its larger device-level capacitance. This combination of a TIGFET's (1) multiple modes of operation, and (2) circuit-level architecture lead to enhanced system performance. In particular, we show that at the 15 nm technology node TIGFET technology has 18% lower energy-delay product for a fan-out of 4 and higher when using 1-bit full-adder logic circuit than for the equivalent node CMOS HP.

中文翻译：

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三独立栅极场效应晶体管的寄生电容分析


三独立栅极场效应晶体管 (TIGFET) 是一种很有前途的替代技术，旨在取代或补充先进技术节点的 CMOS。在本文中，我们使用三维数值模拟提取了硅纳米线 TIGFET 器件的寄生电容和固有电容，试图准确比较其电容，从而在可比节点上与 CMOS 进行电路级性能比较。 TIGFET 晶体管寄生电容的分析模型是使用等效 Schwarz-Christoffel 变换和标准圆柱形电容器等技术得出的，并且与数值模拟非常一致。由于 TIGFET 具有两个额外的栅极触点，TIGFET 晶体管的最大电容比 15 nm CMOS 高性能 (HP) 器件大 2 倍，但这被其多种操作模式的能力所抵消，从而降低了有效开关电容每个设备。与 CMOS HP 器件相比，TIGFET 晶体管的总电容平均仅增加 30%。此外，TIGFET 增加的器件功能可用于修改基于 TIGFET 的设计的电路级架构，以减轻其较大器件级电容的性能影响。 TIGFET (1) 多种操作模式和 (2) 电路级架构的这种组合可增强系统性能。特别是，我们表明，在 15 nm 技术节点，TIGFET 技术在使用 1 位全加器逻辑电路时，对于 4 或更高的扇出，其能量延迟积比等效节点 CMOS HP 低 18%。