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An Open-Source EDA Flow for Asynchronous Logic
IEEE Design & Test ( IF 1.9 ) Pub Date : 2021-01-13 , DOI: 10.1109/mdat.2021.3051334 Samira Ataei 1 , Wenmian Hua 1 , Yihang Yang 1 , Rajit Manohar 2 , Yi-Shan Lu 3 , Jiayuan He 3 , Sepideh Maleki 3 , Keshav Pingali 3
Editor’s note: This article presents an open-source EDA flow for digital asynchronous circuits, capable of supporting many different families of asynchronous circuit families from logic synthesis all the way down to GDSII. — Sherief Reda, Brown University — Leon Stock, IBM — Pierre-Emmanuel Gaillardon, University of Utah
中文翻译:
异步逻辑的开源EDA流程
编者注: 本文介绍了一种用于数字异步电路的开源EDA流程,该流程能够支持从逻辑综合一直到GDSII的许多不同系列的异步电路系列。-布朗大学的谢里夫·雷达(Sherief Reda) - 莱昂·斯托克,IBM - 犹他大学Pierre-Emmanuel Gaillardon
更新日期:2021-01-13
IEEE Design & Test ( IF 1.9 ) Pub Date : 2021-01-13 , DOI: 10.1109/mdat.2021.3051334 Samira Ataei 1 , Wenmian Hua 1 , Yihang Yang 1 , Rajit Manohar 2 , Yi-Shan Lu 3 , Jiayuan He 3 , Sepideh Maleki 3 , Keshav Pingali 3
Affiliation
中文翻译:
异步逻辑的开源EDA流程