Verification is one of the central tasks during circuit design. While most of the approaches have exponential worst-case behaviour, in the following techniques are discussed for proving polynomial circuit verification based on Binary Decision Diagrams (BDDs). It is shown that for circuits with specific structural properties, like e.g. tree-like circuits, and circuits based on multiplexers derived from BDDs complete formal verification can be carried out in polynomial time and space.

中文翻译：

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使用BDD进行多项式电路验证

验证是电路设计过程中的中心任务之一。尽管大多数方法都具有指数最坏情况的行为，但在以下技术中，我们将讨论基于二进制决策图（BDD）证明多项式电路验证的技术。结果表明，对于具有特定结构特性的电路（例如树状电路）以及基于从BDD派生的多路复用器的电路，可以在多项式时间和空间中执行完整的形式验证。