In this paper, we describe the design, layout, and performance of a 6-bit TTD (true time delay) chip operating over the entire band of 2–18 GHz. The 1.15 mm2 chip is implemented using TSMC foundry 65 nm technology. The least significant bit is 1 ps. The design is based on the concept of all-pass network with some modifications intended to reduce the number of unit cells. Thus, the first three bits are implemented in a single delay cell. A peaking buffer amplifier between bit 4 and bit 5 is used for impedance matching and partial compensation of the insertion loss slope. The rms delay error of the TTD is <1 ps over most of the frequency band and insertion loss is between 2.5 and 6.3 dB for all 64 states.

中文翻译：

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65 nm CMOS 中具有低幅度和延迟变化的多倍频程微波 6 位真实时间延迟

在本文中，我们描述了在 2–18 GHz 整个频段上运行的 6 位 TTD（真正的时间延迟）芯片的设计、布局和性能。1.15 毫米2芯片采用台积电代工 65 nm 技术实现。最低有效位为 1 ps。该设计基于全通网络的概念，并进行了一些修改以减少单元格的数量。因此，前三位在单个延迟单元中实现。位 4 和位 5 之间的峰值缓冲放大器用于阻抗匹配和插入损耗斜率的部分补偿。TTD 的 rms 延迟误差在大部分频带上小于 1 ps，所有 64 个状态的插入损耗在 2.5 和 6.3 dB 之间。