Utilizing the layer‐controlled bandgap of a 2D material is an effective way of improving a tunneling field‐effect transistor (TFET) device's performance because of the narrowing tunneling barrier. An ab initio quantum transport method is used to study the SnS homojunction TFETs at a sub‐10 nm scale through layer controlling. The optimal SnS homojunction TFET has a bilayer SnS as the source electrode, which possesses a low leakage current like the ML SnS TFET and a high on‐state current like the BL SnS TFET. The low SS_{ave_4dec} (subthreshold swing over four decades of the drain currents) of ≈47–48 mV dec⁻¹ and I₆₀ (drain current at 60 mV dec⁻¹) of ≈1.1–1.2 µA µm⁻¹ implies the BL source SnS TFET, a fast low‐power (LP) device. The optimal BL source SnS TFET with a gate length of L_g = 10 nm exceeds the LP device requirement of the International Technology Roadmap for Semiconductors (ITRS) (2013 version), and its negative capacitance counterparts can exceed the ITRS 2028 target for LP device at L_g = 5 nm.

中文翻译：

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基于SnS同质结的层控制低功率隧穿晶体管

由于隧穿势垒变窄，利用2D材料的层控制带隙是提高隧穿场效应晶体管（TFET）器件性能的有效方法。从头开始量子传输方法用于通过层控制研究小于10 nm规模的SnS同质结TFET。最佳的SnS同质结TFET以双层SnS作为源极，像ML SnS TFET一样具有低泄漏电流，而像BL SnS TFET一样具有高导通电流。低的SS _{ave_4dec}（漏极电流的四个阈值摆幅）约为≈47-48mV dec ^-1，I ₆₀（约为60 mV dec ^-1时的漏极电流）约为1.1-1.2 µA µm ^-1意味着BL源SnS TFET是一种快速的低功耗（LP）器件。栅极长度为L _g  = 10 nm的最佳BL源SnS TFET超过了国际半导体技术路线图（ITRS）（2013版）的LP器件要求，其负电容可以超过LP器件的ITRS 2028目标在L _g  = 5 nm处。