The 2-D CMOS process technology scaling may have reached its pinnacle, yet it is not feasible to manufacture all computing elements at lower technological nodes. This has opened a new branch of chip designing that allows chiplets on different technological nodes to be integrated into a single package using interposers, the passive interconnection mediums. However, establishing a high-frequency communication over an entirely passive layer is one of the significant design challenges of 2.5-D systems. In this article, we present a robust clocking architecture for a 2.5-D system consisting of 64 processor cores. This clocking scheme consists of two major components, namely, interposer clocking and on-chiplet clocking. The interposer clocking consists of clocks used to achieve global synchronicity and clocks for interchiplet communication established using the AIB protocol. We synthesized these clocking components using commercial EDA tools and analyzed them using standard tools, on-chip, and package models. We also compare these results against a 2-D design of the same benchmark and another 2.5-D clocking architecture. Our experiments show that the absolute clock power is up to 16% less, and the ratio of clock power to system power is up to 4% less in the 2.5-D design than its 2-D counterpart.

中文翻译：

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基于中介层的2.5D异构系统的时钟传输网络设计和分析

2-D CMOS工艺技术的扩展可能已经达到顶峰，但是在较低的技术节点上制造所有计算元件是不可行的。这开启了芯片设计的新分支，该分支允许使用中介层（无源互连介质）将不同技术节点上的小芯片集成到单个封装中。但是，在整个无源层上建立高频通信是2.5-D系统的重大设计挑战之一。在本文中，我们为包含64个处理器内核的2.5D系统提供了一种健壮的时钟体系结构。此时钟方案由两个主要组件组成，即插入器时钟和小芯片上时钟。中介层时钟包括用于实现全局同步的时钟和使用AIB协议建立的小芯片间通信的时钟。我们使用商用EDA工具合成了这些时钟组件，并使用标准工具，片上和封装模型对其进行了分析。我们还将这些结果与具有相同基准的2-D设计和另一个2.5-D时钟架构进行比较。我们的实验表明，在2.5D设计中，绝对时钟功率比其2-D同类产品少了16％，并且时钟功率与系统功率之比也比其少了4％。