This article presents a hardware-friendly algorithm and architecture for cooperative spectrum sensing (CSS) in the data-fusion-based cognitive-radio (CR) network. The proposed VLSI-algorithm is based on the iterative power method and deflation technique that alleviate the computational complexity of conventional CSS algorithm with minimal performance degradation. In this work, a new hardware-efficient VLSI architecture of cooperative spectrum sensor (CSR) for the data-fusion center is presented, which supports up to six secondary users in the cooperative CR network. Its performance analysis under fading channel environment has been carried out where it delivers 0.8 detection probability ( $P_{d}$ ) at −8 dB of channel SNR with a false alarm rate of 0.1. It shows the minimum performance degradation of 0.057 dB at $P_{d} = 0.88$ compared to the conventional algorithm. The suggested CSR architecture has been application-specific integrated circuit (ASIC)-synthesized and postlayout simulated in UMC 90 nm-CMOS process. Thus, it occupies 2.4 mm ² of the core area, consumes 36 mW of total power, and delivers a low sensing time of $60.41~\mu \text{s}$ while operating at a maximum clock frequency of 87.7 MHz. Comparison with the reported works indicates that the proposed design requires 40.3% lesser area, and it is 41% hardware efficient than the conventional implementation. Eventually, this design has been field-programmable gate array (FPGA) prototyped, and its functionality is verified in the real-world test environment.

中文翻译：

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基于数据融合的协作式认知无线电网络的新型硬件有效频谱传感器VLSI架构

本文介绍了一种基于硬件的算法和体系结构，用于基于数据融合的认知无线电（CR）网络中的协作频谱感知（CSS）。所提出的VLSI算法基于迭代幂方法和放气技术，其以最小的性能降低来减轻常规CSS算法的计算复杂性。在这项工作中，提出了一种用于数据融合中心的新型硬件效率更高的协作频谱传感器（CSR）的VLSI架构，该架构可在协作CR网络中最多支持六个次要用户。在衰落信道环境下进行了性能分析，并提供了0.8的检测概率（ $ P_ {d} $ ）在通道SNR的-8 dB时，误报率为0.1。它显示出在0.057 dB时的最小性能下降 $ P_ {d} = 0.88 $ 与传统算法相比 建议的CSR体系结构已通过专用集成电路（ASIC）进行了合成，并以UMC 90 nm-CMOS工艺进行了后布局仿真。因此，它占据了核心面积的2.4 mm ²，消耗了36 mW的总功率，并提供了很短的感测时间。 $ 60.41〜\ mu \ text {s} $ 同时以87.7 MHz的最大时钟频率运行。与已报道的工作进行比较表明，所提出的设计所需的面积减少了40.3％，并且其硬件效率比传统实施方案低41％。最终，该设计已通过现场可编程门阵列（FPGA）进行了原型设计，其功能已在实际测试环境中得到了验证。