Logic gates are designed using symmetric lateral doping-free bipolar junction transistor (BJT) on silicon on insulator (SOI) using differential pass transistor logic, and their performance matrices are presented. Charge carriers are induced in lightly doped emitter and collector regions using two unique approaches. i.e., the charge plasma (CP) and polarity control (PC). AND, OR and XOR gates are designed using four types of devices (CP-NPN, CP-PNP, PC-NPN, and PC-PNP) and transient and noise margin analysis are performed. The transient response shows rise and fall time less than 100 ps while worst-case noise margin of 0.25 V observed for an input voltage of 1 V. Moreover, 2:1 multiplexer is also designed and explored for output transient and voltage levels. The delay of less than 2.2 ns is achieved with a nominal deviation of 0.1 V and 0.04 V for high and low output levels respectively.

使用差分传输晶体管逻辑，在绝缘体上硅（SOI）上使用对称横向无掺杂双极结型晶体管（BJT）设计逻辑门，并介绍了它们的性能矩阵。使用两种独特的方法在轻掺杂的发射极和集电极区域中感应出电荷载流子。即，电荷等离子体（CP）和极性控制（PC）。使用四种类型的器件（CP-NPN，CP-PNP，PC-NPN和PC-PNP）设计AND，OR和XOR门，并进行瞬态和噪声容限分析。瞬态响应显示上升和下降时间小于100 ps，而在1 V输入电压下观察到的最坏情况下的噪声裕度为0.25V。此外，还针对输出瞬态和电压电平设计并探索了2：1多路复用器。标称偏差为0.1 V和0时，可实现小于2.2 ns的延迟。