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Real-Time FPGA Implementation of Parallel Connected Component Labelling for a 4K Video Stream
Journal of Signal Processing Systems ( IF 1.6 ) Pub Date : 2021-04-01 , DOI: 10.1007/s11265-021-01636-4
Marcin Kowalczyk , Piotr Ciarach , Dominika Przewlocka-Rus , Hubert Szolc , Tomasz Kryjak

In this paper, a hardware implementation in reconfigurable logic of a single-pass connected component labelling (CCL) and connected component analysis (CCA) module is presented. The main novelty of the design is the support of a video stream in 2 and 4 pixel per clock format (2 and 4 ppc) and real-time processing of 4K/UHD video stream (3840 x 2160 pixels) at 60 frames per second. We discuss several approaches to the issue and present in detail the selected ones. The proposed module was verified in an exemplary application – skin colour areas segmentation – on the ZCU 102 and ZCU 104 evaluation boards equipped with Xilinx Zynq UltraScale+ MPSoC devices.



中文翻译:

4K视频流的并行连接组件标记的实时FPGA实现

在本文中,提出了一种可重构逻辑中的单通道连接组件标记(CCL)和连接组件分析(CCA)模块的硬件实现。该设计的主要新颖之处在于支持每个时钟格式2和4像素(2和4 ppc)的视频流,以及每秒60帧的4K / UHD视频流(3840 x 2160像素)的实时处理。我们讨论了解决该问题的几种方法,并详细介绍了所选择的方法。所建议的模块已在配备Xilinx Zynq UltraScale + MPSoC器件的ZCU 102和ZCU 104评估板上的示例性应用(肤色区域分割)中得到了验证。

更新日期:2021-04-01
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