ABSTRACT

This paper presents a single-ended 9T SRAM cell with data-aware write-word-line structure to improve write ability, and a positive feedback sense amplifier (SA) to solve sensing challenge at an ultra-low voltage. The proposed 9T cell is well suited for bit-interleaving architecture in SRAM array. Simulation results indicate that at a 0.5 V supply voltage, the proposed SRAM cell achieves the same read static noise margin (RSNM) as that of conventional 8T SRAM cell, because the read-decoupled read buffer achieves read-disturb-free operation. While at the same supply voltage, its write margin (WM) is 2.68× compared with the 8T SRAM cell. As a result, a lower minimum operation voltage is achieved. Additionally, its leakage power consumption is reduced by 86.1% compared with the 8T SRAM cell in the 40-nm standard CMOS technology, TT corner, 25°C.

摘要

本文介绍了一种具有数据感知写入字线结构的单端 9T SRAM 单元以提高写入能力，以及一种正反馈读出放大器 (SA) 以解决超低电压下的读出挑战。所提出的 9T 单元非常适合 SRAM 阵列中的位交错架构。仿真结果表明，在 0.5 V 电源电压下，所提出的 SRAM 单元实现了与传统 8T SRAM 单元相同的读取静态噪声容限 (RSNM)，因为读取去耦读取缓冲器实现了无读取干扰操作。在相同电源电压下，其写入裕量 (WM) 是 8T SRAM 单元的 2.68 倍。结果，实现了较低的最小工作电压。此外，其漏电功耗比采用40纳米标准CMOS工艺、TT角、25°C的8T SRAM单元降低了86.1%。