The design of low power memory cells is the dream of engineers in memory design. A Darlington-based 8T CNTFET SRAM cell is suggested in this paper. It is called the proposed P_CNTFET Darlington 8T SRAM Cell. Compared with that of the traditional 6T and 8T CNTFET SRAM cells, the power and noise performances of the proposed SRAM cell are comparable. Compared to the traditional SRAM cells, the write, hold, read and dynamic power consumption of the proposed cell is much lower. The CNTFET parameters are optimized to boost the noise margin performance of the suggested bit cell. For optimized parameters, the power consumption and SNM of the proposed cell are compared with conventional cells. In contrast to the conventional cells, the HSNM and WSNM of the proposed cell are improved by 6.25% and 66.6%. The proposed cell’s RSNM is 38% greater than the traditional 6T SRAM cell. The proposed cell’s RSNM is 3.33% less than the traditional 8T SRAM cell. MOSFET is also used to implement the proposed SRAM cell and its noise margin and power performance are compared with traditional MOSFET-based SRAM cells. As with the conventional cells, the MOSFET-based implementation of the proposed cell power and SNM performance is also very good. The simulation is done with the HSPICE simulation tool using the Stanford University 32nm CNTFET model.

中文翻译：

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用于低功耗应用的新型基于达林顿的 8T CNTFET SRAM 单元

低功耗存储单元的设计是存储器设计工程师的梦想。本文建议使用基于达林顿的 8T CNTFET SRAM 单元。它被称为提议的 P_CNTFET Darlington 8T SRAM 单元。与传统的 6T 和 8T CNTFET SRAM 单元相比，所提出的 SRAM 单元的功率和噪声性能相当。与传统的 SRAM 单元相比，该单元的写入、保持、读取和动态功耗要低得多。CNTFET 参数经过优化以提高建议位单元的噪声容限性能。为了优化参数，将所提出的小区的功耗和 SNM 与传统小区进行了比较。与传统小区相比，该小区的 HSNM 和 WSNM 分别提高了 6.25% 和 66.6%。提议的单元的 RSNM 比传统的 6T SRAM 单元大 38%。建议单元的 RSNM 比传统的 8T SRAM 单元低 3.33%。MOSFET 也用于实现所提出的 SRAM 单元，并将其噪声容限和功率性能与传统的基于 MOSFET 的 SRAM 单元进行比较。与传统电池一样，基于 MOSFET 的电池功率和 SNM 性能也非常好。仿真是使用斯坦福大学的 HSPICE 仿真工具完成的 32 建议的基于 MOSFET 的电池功率和 SNM 性能也非常好。仿真是使用斯坦福大学的 HSPICE 仿真工具完成的 32 建议的基于 MOSFET 的电池功率和 SNM 性能也非常好。仿真是使用斯坦福大学的 HSPICE 仿真工具完成的 32纳米 CNTFET 模型。