Convolutional neural networks (CNNs) have shown appealing performance on stereo matching tasks in recent years. However, existing deep neural networks (DNNs) based matching algorithms use semi-global matching (SGM) to aggregate the matching costs, which limit the processing speed. In this study, we present a novel binarized CNN stereo matching hardware acceleration using local methods on an FPGA, which can provide high accuracy stereo estimation and achieve high-throughput at the same time. To reduce the consumption of hardware resource and improve the processing speed, we propose pipelined architecture for BNN, and sparse local aggregation to optimize the implementation on an FPGA. We evaluated the proposed implementation on a challenging stereo dataset with a Stratix V FPGA. From the experimental results, our binarized CNN stereo matching implementation shows significant improvement in the real-time performance and the energy efficiency over other computing platforms with a 6.95% error rate on the KITTI2015 dataset.

近年来，卷积神经网络（CNN）在立体匹配任务上表现出了诱人的性能。但是，现有的基于深度神经网络（DNN）的匹配算法使用半全局匹配（SGM）来汇总匹配成本，这限制了处理速度。在这项研究中，我们提出了一种新颖的二进制化CNN立体声匹配硬件加速，使用FPGA上的本地方法，可以提供高精度的立体声估计并同时实现高吞吐量。为了减少硬件资源的消耗并提高处理速度，我们提出了一种用于BNN的流水线架构，并通过稀疏局部聚合来优化FPGA上的实现。我们使用Stratix V FPGA在具有挑战性的立体声数据集上评估了建议的实现。从实验结果来看