A triple modular redundancy SRAM was designed as the embedded high-speed memory for a radiation-tolerant ARM processor with ST Microelectronics 28-nm FDSOI technology. The single event upset (SEU) cross-section of the SRAM was tested by using heavy ions with the linear energy transfer of 15.0 meV.cm².mg⁻¹ in both non-TMR and TMR modes with different accumulated fluence. The SRAM cell was also simulated by using Cogenda TCAD simulation suite and the cross section was calculated by using analytic method. The results showed the cross-section is around 2E-10 cm²/bit in non-TMR mode, and in TMR mode it varied from one to several orders lower than the non-TMR mode according to the specific accumulated fluence. As a scrubbing circuit was designed to reduce the accumulated number of SEUs in the SRAM, the Failure In Time (FIT) rate at sea level in New York City could be as low as 8E-11, which is robust enough for the whole circuit.

三重模块化冗余SRAM被设计为采用ST Microelectronics 28纳米FDSOI技术的耐辐射ARM处理器的嵌入式高速存储器。通过在非TMR和TMR模式下使用具有不同累积通量的线性能量转移为15.0 meV.cm ² .mg ^-1的重离子，测试SRAM的单事件翻转（SEU）横截面。还使用Cogenda TCAD仿真套件对SRAM单元进行了仿真，并使用解析方法计算了横截面。结果表明，横截面约为2E-10 cm ²/ TM在非TMR模式下为/ bit，而在TMR模式下，根据特定的累积通量，它比非TMR模式低一个到几个数量级。由于设计了一种擦洗电路以减少SRAM中SEU的累积数量，因此纽约市海平面的时间故障率（FIT）可能低至8E-11，这对于整个电路来说足够坚固。