The proposal of the ubiquitous power Internet of Things (UPIoT) has increased the demand for communication coverage and data collection of smart grid; the quantity and quality of communication networks are facing greater challenges. This brief applies (73, 37, 13) quadratic residue (QR) codes to power line carrier technology to improve the quality of local data communication in UPIoT. In order to improve the decoding performance of the QR codes, an induction method for the error pattern is proposed, which can divide the originally coupled error pattern into six parts and reuse the same module for decoding. This method greatly reduces the resource requirements, so that (73, 37, 13) QR code can be implemented on FPGA hardware. Notably, the hardware architecture is a modular framework, which can fit into an FPGA with different sizes. As an example (73, 37, 13), QR code is implemented on Intel Arria10 FPGA; the experimental result shows that the maximum decoding frequency of this architecture is 21.7 M Hz, which achieves 4121x speedup compared to CPU. Moreover, the proposed architecture benefits from high flexibility, such as modular design and decoding framework in the form of the pipeline which can be seen as an alternative scheme for decoding long-length QR codes.

中文翻译：

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UPIoT中用于电力线载波的（73、37、13）QR码的硬件解码加速器

通用的物联网（UPIoT）的提议增加了对智能电网的通信覆盖和数据收集的需求。通信网络的数量和质量面临更大的挑战。本简介将（73、37、13）二次余数（QR）代码应用于电力线载波技术，以提高UPIoT中本地数据通信的质量。为了提高QR码的解码性能，提出了一种错误码型的归纳方法，该方法可以将原始耦合的错误码型分为六个部分，并重复使用相同的模块进行解码。这种方法大大减少了资源需求，因此可以在FPGA硬件上实现（73，37，13）QR码。值得注意的是，硬件架构是一个模块化框架，可以适合具有不同大小的FPGA。例如（73、37、13），QR码是在Intel Arria10 FPGA上实现的。实验结果表明，该架构的最大解码频率为21.7 M Hz，与CPU相比，可实现4121倍的加速。此外，所提出的架构得益于高度的灵活性，例如以流水线形式的模块化设计和解码框架，可以将其视为解码长QR码的替代方案。