In this work, we propose and investigate a new pocket-based Si_0.55Ge_0.45/Si gate normal tunnel FET design employing a gate over source with a single lateral pocket (GSLP) with and without a heterogeneous dielectric (HD) gate oxide. Miller capacitance is significantly reduced with the GSLP design, which is further improved by the HD gate oxide leading to full overshoot/undershoot suppression capability in transient response. Further, a steep switching with more than one order improvement in ON current is achieved when compared to state-of-the-art line pocket designs. As a result, an ~98.8% and ~88% improved intrinsic delay (C_GGV_DD/I_ON) is achieved in comparison to dual line pocket and non-pocketed designs, respectively. Additionally, an improved worst-case trap-charge tolerance, reduced pocket-width-induced fluctuations, and excellent immunity to gate misalignment-induced fluctuations are achievable just by replacing the gate-aligned parallel-line pockets with a vertically aligned single-lateral pocket (LP) improving the design reliability. A Ge/Si HD-GSLP TFET design further offers stable ON currents with SS < 60 mV/dec over a feasible range of pocket widths between ~6 and 8 nm at V_DS = V_GS = 0.7 V.

中文翻译：

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异质电氧化物设计的单侧袋式门控源 TFET

在这项工作中，我们提出并研究了一种新的基于口袋的 Si _0.55 Ge _0.45 /Si 栅极正常隧道 FET 设计，该设计采用带有和不具有异质电介质 (HD) 栅极氧化物的单个横向口袋 (GSLP) 的源极上栅极。GSLP 设计显着降低了米勒电容，而 HD 栅极氧化物进一步改善了这一点，从而在瞬态响应中实现了完全的过冲/下冲抑制能力。此外，与最先进的线袋设计相比，实现了导通电流提高超过一个数量级的陡峭开关。因此，固有延迟提高了约 98.8% 和约 88% ( C _GG V _DD / I _ON) 分别与双线口袋和非口袋设计相比实现。此外，只需将栅极对齐的平行线袋替换为垂直对齐的单侧袋，即可实现改进的最坏情况陷阱电荷容限、减少袋宽度引起的波动以及对栅极未对准引起的波动的出色免疫力(LP) 提高设计可靠性。Ge/Si HD-GSLP TFET 设计进一步提供稳定的导通电流，SS < 60 mV/dec 在V _DS  =  V _GS  = 0.7 V 时~6 到 8 nm 的口袋宽度的可行范围内。