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Test Generation for Hardware Trojan Detection Using Correlation Analysis and Genetic Algorithm
ACM Transactions on Embedded Computing Systems ( IF 2 ) Pub Date : 2021-03-26 , DOI: 10.1145/3446837
Zhendong Shi 1 , Haocheng Ma 1 , Qizhi Zhang 1 , Yanjiang Liu 1 , Yiqiang Zhao 1 , Jiaji He 2
Affiliation  

Hardware Trojan (HT) is a major threat to the security of integrated circuits (ICs). Among various HT detection approaches, side channel analysis (SCA)-based methods have been extensively studied. SCA-based methods try to detect HTs by comparing side channel signatures from circuits under test with those from trusted golden references. The pre-condition for SCA-based HT detection to work is that the testers can collect extra signatures/anomalies introduced by activated HTs. Thus, activation of HTs and amplification of the differences between circuits under test and golden references are the keys to SCA-based HT detection methods. Test vectors are of great importance to the activation of HTs, but existing test generation methods have two major limitations. First, the number of test vectors required to trigger HTs is quite large. Second, the HT circuit’s activities are marginal compared with the whole circuit’s activities. In this article, we propose an optimized test generation methodology to assist SCA-based HT detection. Considering the HTs’ inherent surreptitious nature, inactive nodes with low transition probability are more likely to be selected as HT trigger nodes. Therefore, the correlations between circuit inputs and inactive nodes are first exploited to activate HTs. Then a test reordering process based on the genetic algorithm (GA) is implemented to increase the proportion of the HT circuit’s activities to the whole circuit’s activities. Experiments on 10 selected ISCAS benchmarks, wb_conmax benchmark, and b17 benchmark demonstrate that the number of test vectors required to trigger HTs reduces 28.8% on average compared with the result of MERO and MERS methods. After the test vector reordering process, the proportion of the HT circuit’s activities to the whole circuit’s activities is improved by 95% on average, compared with the result of MERS method.

中文翻译:

使用相关分析和遗传算法进行硬件木马检测的测试生成

硬件木马 (HT) 是集成电路 (IC) 安全的主要威胁。在各种 HT 检测方法中,基于侧信道分析 (SCA) 的方法已得到广泛研究。基于 SCA 的方法尝试通过将来自被测电路的侧信道特征与来自受信任的黄金参考的侧信道特征进行比较来检测 HT。基于 SCA 的 HT 检测工作的先决条件是测试人员可以收集由激活的 HT 引入的额外签名/异常。因此,激活 HT 和放大被测电路与黄金参考之间的差异是基于 SCA 的 HT 检测方法的关键。测试向量对 HT 的激活非常重要,但现有的测试生成方法有两个主要限制。首先,触发 HT 所需的测试向量数量非常大。第二,与整个电路的活动相比,HT 电路的活动是微不足道的。在本文中,我们提出了一种优化的测试生成方法来辅助基于 SCA 的 HT 检测。考虑到 HT 固有的隐秘性,转移概率低的非活动节点更有可能被选为 HT 触发节点。因此,首先利用电路输入和非活动节点之间的相关性来激活 HT。然后实施基于遗传算法(GA)的测试重新排序过程,以增加HT电路活动在整个电路活动中的比例。对 10 个选定的 ISCAS 基准、wb_conmax 基准和 b17 基准的实验表明,与 MERO 和 MERS 方法的结果相比,触发 HT 所需的测试向量数量平均减少了 28.8%。
更新日期:2021-03-26
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