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FPGA-based implementation of two-step schedulers for modular optical interconnection networks
Journal of Optical Communications and Networking ( IF 4.0 ) Pub Date : 2021-03-23 , DOI: 10.1364/jocn.417897
Justine Cris Borromeo 1 , Isabella Cerutti 1, 2 , Piero Castoldi 1 , Rosula Reyes 3 , Nicola Andriolli 4
Affiliation  

Optical interconnection networks promise to overcome the limitations of current electronic switching fabrics, enabling higher throughput, lower latency, and lower power consumption. Multi-plane architectures, based on multiple optical switching domains (e.g., space, time, wavelength, orbital angular momentum), are gaining research attention because of their modularity and scalability compared to single-domain switches. An effective scheduler, namely, the two-step scheduler (TSS), has been proposed for multi-plane optical interconnection networks, exploiting their modularity to speed up computations while satisfying the peculiar scheduling constraints. In this paper, a hardware implementation of TSS for modular optical interconnection networks is presented and thoroughly assessed. Both scheduling steps are parallelized with the aim of optimizing the execution time. iSLIP and longest queue first (LQF) scheduling algorithms are exploited in each step, resulting in four TSS configurations that are compared among each other and with classical single-step schedulers (SSSs) in terms of scheduling and hardware performance. TSS outperforms SSS in terms of the number of iterations, maximum operating frequency, worst-case scheduling duration, and required logic resources (i.e., scalability) at the expense of a slight latency penalty. Among all TSS configurations, LQF-based TSS guarantees the lowest scheduling latency, while iSLIP-based TSS minimizes the scheduling duration and the use of field programmable gate array (FPGA) resources.

中文翻译:

基于FPGA的模块化光纤互连网络两步调度程序的实现

光互连网络有望克服当前电子交换结构的局限性,从而实现更高的吞吐量,更低的等待时间和更低的功耗。基于多个光交换域(例如,空间,时间,波长,轨道角动量)的多平面架构由于其模块化和可扩展性而比单域交换机具有更高的研究关注度。对于多平面光互连网络,已经提出了一种有效的调度程序,即两步调度程序(TSS),利用它们的模块化来加快计算速度,同时满足特殊的调度约束。在本文中,提出并全面评估了用于模块化光互连网络的TSS的硬件实现。为了优化执行时间,两个调度步骤并行进行。在每个步骤中都使用了iSLIP和最长队列优先(LQF)调度算法,从而产生了四个TSS配置,它们在调度和硬件性能方面相互比较,并与传统的单步调度程序(SSS)进行了比较。在迭代次数,最大工作频率,最坏情况下的调度持续时间和所需的逻辑资源(即,可伸缩性)方面,TSS优于SSS,但代价是稍有延迟。在所有TSS配置中,基于LQF的TSS保证了最低的调度等待时间,而基于iSLIP的TSS则使调度持续时间和现场可编程门阵列(FPGA)资源的使用最小化。在每个步骤中都使用了iSLIP和最长队列优先(LQF)调度算法,从而产生了四个TSS配置,它们在调度和硬件性能方面相互比较,并与传统的单步调度程序(SSS)进行了比较。在迭代次数,最大工作频率,最坏情况下的调度持续时间和所需的逻辑资源(即,可伸缩性)方面,TSS优于SSS,但代价是稍有延迟。在所有TSS配置中,基于LQF的TSS保证了最低的调度等待时间,而基于iSLIP的TSS则使调度持续时间和现场可编程门阵列(FPGA)资源的使用最小化。在每个步骤中都使用了iSLIP和最长队列优先(LQF)调度算法,从而产生了四个TSS配置,它们在调度和硬件性能方面相互比较,并与传统的单步调度程序(SSS)进行了比较。在迭代次数,最大工作频率,最坏情况下的调度持续时间和所需的逻辑资源(即,可伸缩性)方面,TSS优于SSS,但代价是稍有延迟。在所有TSS配置中,基于LQF的TSS保证了最低的调度等待时间,而基于iSLIP的TSS则使调度持续时间和现场可编程门阵列(FPGA)资源的使用最小化。在迭代次数,最大工作频率,最坏情况下的调度持续时间和所需的逻辑资源(即,可伸缩性)方面,TSS优于SSS,但代价是稍有延迟。在所有TSS配置中,基于LQF的TSS保证了最低的调度等待时间,而基于iSLIP的TSS则使调度持续时间和现场可编程门阵列(FPGA)资源的使用最小化。在迭代次数,最大工作频率,最坏情况下的调度持续时间和所需的逻辑资源(即,可伸缩性)方面,TSS优于SSS,但代价是稍有延迟。在所有TSS配置中,基于LQF的TSS保证了最低的调度等待时间,而基于iSLIP的TSS则使调度持续时间和现场可编程门阵列(FPGA)资源的使用最小化。
更新日期:2021-03-26
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