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An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks
IEEE Journal of Solid-State Circuits ( IF 4.6 ) Pub Date : 2020-12-14 , DOI: 10.1109/jssc.2020.3041858
Hyochan An , Sam Schiferl , Siddharth Venkatesan , Tim Wesley , Qirui Zhang , Jingcheng Wang , Kyojin D. Choo , Shiyu Liu , Bowen Liu , Ziyun Li , Luyao Gong , Hengfei Zhong , David Blaauw , Ronald Dreslinski , Hun Seok Kim , Dennis Sylvester

We propose an ultra-low-power (ULP) image signal processor (ISP) that performs on-the-fly in-processing frame compression/decompression and hierarchical event recognition to exploit the temporal and spatial sparsity in an image sequence. This approach reduces energy consumption spent processing and transmitting unimportant image data to achieve a 16 $\times $ imaging system energy gain in an intruder detection scenario. The ISP was fabricated in 40-nm CMOS and consumes only 170 $\mu \text{W}$ at 5 frames/s for neural network-based intruder detection and 192 $\times $ compressed image recording.

中文翻译:

用于深层神经网络的分层图像识别的超低功耗图像信号处理器

我们提出了一种超低功耗(ULP)图像信号处理器(ISP),该处理器执行动态处理中帧压缩/解压缩和分层事件识别,以利用图像序列中的时间和空间稀疏性。这种方法减少了处理和传输不重要的图像数据以达到16 $ \次$ 入侵者检测场景中的成像系统能量增益。ISP采用40纳米CMOS制造,仅消耗170 $ \ mu \ text {W} $ 以5帧/秒的速度用于基于神经网络的入侵者检测和192 $ \次$ 压缩图像记录。
更新日期:2020-12-14
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