This article presents a 1.2-V, 1.8-Gb/s/pin 16-Tb NAND flash memory multi-chip package incorporating 16 dies of 1-Tb NAND flash memory and the third-generation F-chip. The proposed third-generation F-chip is developed to meet the performance requirements of a high-capacity storage device that adopts a PCIe Gen four-host interface for higher data throughput. It is implemented with dual bi-directional transceiver architecture and signal retiming scheme to maximize the valid data window opening on solid-state drive (SSD) channels. Also, it facilitates training between F-chip and NAND using an on-chip delay-locked loop whose locking is proposed in strobe-based NAND systems to achieve sufficient signal integrity (SI) of the in-package channel at a speed of 1.8 Gb/s/pin. Embedded built-in self-test evaluates un-selected paths and determines if re-training is required without losing data throughput performance. This work achieves a 35% improvement in the I/O operational speed performance and a 23% reduction in the I/O power consumption in comparison with the previous generations.

中文翻译：

---

具有F芯片的1.8 Gb / s / Pin 16 Tb NAND闪存多芯片封装，用于高性能和大容量存储

本文介绍了一种1.2V，1.8-Gb / s / pin的16-Tb NAND闪存多芯片封装，其中包含16个1-Tb NAND闪存和第三代F芯片。拟议中的第三代F芯片旨在满足采用PCIe Gen四主机接口以实现更高数据吞吐量的大容量存储设备的性能要求。它采用双向双向收发器体系结构和信号重定时方案来实现，以最大程度地提高固态驱动器（SSD）通道上的有效数据窗口打开率。此外，它还有助于使用片上延迟锁定环在F芯片和NAND之间进行训练，该延迟锁定环在基于选通的NAND系统中提出，旨在以1.8 Gb的速度实现封装内通道的足够信号完整性（SI） /旋转。嵌入式内置自测功能可评估未选择的路径，并确定是否需要重新训练，而不会损失数据吞吐性能。与前几代产品相比，这项工作使I / O操作速度性能提高了35％，I / O功耗降低了23％。